Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC
Vishal Baskar, Siemens Industry Software Inc – Siemens EDA
Novel GUI Based UVM Test Bench Template Builder
Vignesh Manoharan, Aeva
Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification
Victor Besyakov, Untether AI
Modeling Analog Devices using SV-RNM
Mariam Maurice, Siemens EDA (formerly Mentor Graphics)
Successive Refinement – An approach to decouple Front-End and Back-end Power Intent
Kavya Kotha, Intel Technology Pvt Ltd Rohit Kumar Sinha, Intel Technology Pvt Ltd
Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges
Rohit Sinha, Intel Kavya Kotha, Intel
Hybrid Emulation: Accelerating Software driven Verification and Debug
Issac Zacharia, Arm Ltd Jitendra Aggarwal, Arm Ltd
Confidently Sign-off any Low-Power Designs without Consequences
Madhur Bhargava, Siemens EDA Jitesh Bonshal, Siemens EDA Progyna Khondkar, Siemens EDA
A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation
Thomas Soong, Intel Chenhui Huang, Intel Christopher Browne, Intel
Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform
Neeraj Gupta, Intel Technology India Pvt Ltd Reddaiah Yedoti, Intel Technology India Pvt Ltd Dixit Sethi, Intel Technology India Pvt Ltd Sarvesh Kumar Pandey, Intel Technology India Pvt Ltd
