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Menu
  • Home
  • About
    • Steering Committee
    • Technical Program Committee
    • History & Archive
    • DVCon U.S. Conference Sponsor & Privacy Policy
  • Author / Speaker Information
    • Abstract Submissions
    • Tutorial/Workshop Submissions
    • Panel Submissions
    • Speaker Resources and Guidelines
    • Pre-Recorded Video Instructions
  • Sponsors & Exhibitors
    • Sponsor & Exhibitor Resources
    • 2023 Sponsors
    • 2023 Exhibitors
  • Program
    • 2023 Program Grid
    • Keynote: Dirk Didascalou
    • Panel: Systems are Evolving. Is Verification Keeping Up?
    • Panel: AI-ML Algorithms are Transforming Verification: Separating Hype from Reality
    • 2023 Accepted Papers
    • 2022 Program Information
      • Welcome Message from the General Chair
      • Program Grid
      • Keynote: Manish Pandey
      • Stuart Sutherland Best Paper & Best Poster Award Recipients
      • 2022 Sponsors & Exhibitors
      • Virtual Exhibit Hall (Gather.Town)
  • Registration
  • Hotel & Travel
  • Media
    • News
      • Press Release – December 8, 2022
      • Press Release – June 8, 2022
      • Press Release – May 24, 2022
      • Press Release – March 8, 2022
      • Breakfast Bytes – February 22, 2022
      • Press Release – February 22, 2022
      • EDA Café: 2022 General Chair Interview
      • SemiWiki: 2022 Gather.Town and Accellera Coverage
      • EE Journal Fish Fry – February 11, 2022
      • Press Release – February 8, 2022
      • Press Release – December 8, 2021
      • Press Release – October 12, 2021
      • Press Release – July 28, 2021
      • Press Release – July 12, 2021
    • Videos
    • Photos
      • DVCon US 2018 Photos
      • DVCon US 2017 Photos

Presenter Type: Poster

Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC

Vishal Baskar, Siemens Industry Software Inc – Siemens EDA

Novel GUI Based UVM Test Bench Template Builder

Vignesh Manoharan, Aeva

Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification

Victor Besyakov, Untether AI

Modeling Analog Devices using SV-RNM

Mariam Maurice, Siemens EDA (formerly Mentor Graphics)

Successive Refinement – An approach to decouple Front-End and Back-end Power Intent

Kavya Kotha, Intel Technology Pvt Ltd Rohit Kumar Sinha, Intel Technology Pvt Ltd

Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges

Rohit Sinha, Intel Kavya Kotha, Intel

Hybrid Emulation: Accelerating Software driven Verification and Debug

Issac Zacharia, Arm Ltd Jitendra Aggarwal, Arm Ltd

Confidently Sign-off any Low-Power Designs without Consequences

Madhur Bhargava, Siemens EDA Jitesh Bonshal, Siemens EDA Progyna Khondkar, Siemens EDA

A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation

Thomas Soong, Intel Chenhui Huang, Intel Christopher Browne, Intel

Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform

Neeraj Gupta, Intel Technology India Pvt Ltd Reddaiah Yedoti, Intel Technology India Pvt Ltd Dixit Sethi, Intel Technology India Pvt Ltd Sarvesh Kumar Pandey, Intel Technology India Pvt Ltd

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