FuSa: An Update on the Accellera Functional Safety Standard
By: Alessandra Nardi, Accellera Functional Safety Working Group Chair Darren Galpin, Principal Digital Verification Engineer @ Renesas Vatsa Prahallada, Technical Director, Design Enablement @ NXP Semiconductors
UVM-AMS: An Update on the Accellera UVM
Tom Fitzpatrick Accellera UVM-AMS Working Group
Leveraging Virtual Platforms to Shift-Left Software Development and System Verification
Ross Dickson Cadence Design Systems Pankaj Kakkar Cadence Design Systems
An Overview of Security Annotation for Electronic Design Integration (SA-EDI) Standard
Sohrab Aftabjahani, member of the IP Security Assurance Working Group Senior Staff Security Researcher, PhD, SIM, SAM, Intel Corporation
UVVM: Bringing UVM to VHDL
Espen Tallaksen EmLogic Norway
Proven Strategies for Better Verification Planning
Authors: Jeff McNeal, Jeff Vance, Paul Marriott; Verilab, Inc.
In-emulator UVM++ Randomized Testbenches for High Performance Functional Verification
David Kelf
Estimating Power Dissipation of End-User Application on RTL
Kevin G. Hotaling, Sr. Director S2S R&D Magdy A. El-Moursy, Sr. Engineering Manager Solution Prototypes
IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes!
Amanjyot Kaur Agnisys Neena Chandawale Agnisys Anupam Bakshi Agnisys
Building a Comprehensive Hardware Security Methodology
Anders Nordstrom Tortuga Logic Jagadish Nayak Tortuga Logic
