A Comparative Study of CHISEL and SystemVerilog, Based on Logical Equivalent SweRV-EL2 RISC-V Core

A detailed comparative study is done over Western digital SweRV-EL2 implemented in SystemVerilog (2009) with its logical equivalent implementation in CHISEL (Constructing Hardware In Scala Embedded Language). The CHISEL version of the SweRV-EL2 implemented by us is “Quasar”. The key metrics for qualitative comparison are code readability, code density, and code maintenance whereas for quantitative comparison are silicon area, maximum operating frequency, and dynamic power.

Junaid Ahmed, Lampro Mellon
Waleed Bin Ehsan, Lampro Mellon
Laraib Khan, Lampro Mellon
Asad Aleem, Lampro Mellon
Agha Ali Zeb, Lampro Mellon
Sarmad Paracha, Lampro Mellon
Abdul Hameed Akram, Lampro Mellon
Aashir Ahsan, Lampro Mellon