Since born in 2010, RISC-V has been gained more and more popularity. RISC-V vector extension (RVV) as a standard extension was introduced to enhance its capability for AI applications. RVV requires more complex exception and hazard handling, which raises a big challenge for verification. In this paper, we will demonstrate a practical hybrid verification solution to RVV. A flexible and automated instruction modeling flow is proposed to catch up with the continuous evolution of RISC-V instructions. For exception’s verification, a UVM-based solution is adopted to satisfy the requirement of RVV instruction’s contextual relevance. For hazard handling, a simulation & formal hybrid solution is adopted to achieve better design quality with less simulation resources.