A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings
The need for preventing data skew in digital designs is well known in the industry, and standard simulation or formal checks ensure that these functional bugs don’t reach silicon. However, by labelling Clock Domain Crossing (CDC) signals as “false paths,” different bits of a CDC bus or its qualifier may be routed with varying amounts of time delay. If the delay on certain bits is greater than 1 clock cycle, this can result in data skew or metastability in the sampling. Such issues can create silicon-killing functional bugs, and since these timing issues don’t appear in RTL simulation, designers need to spend a large amount of effort to identify and constrain these paths for the back-end. This paper will describe new and improved methodologies for detecting and preventing such timing-analysis CDC bugs that also remove the overhead from designers.