A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example

A simple way of extending the UVM framework to verify an analog/mixed-signal device-under-test (DUT) is presented. A digitally-programmable analog bandpass filter circuit serves as an example. The SystemVerilog UVM testbench presented checks the filter’s transfer gain at randomly-chosen frequencies against the values predicted by SPICE. It collects the results in a UVM-based scoreboard. It uses SystemVerilog assertions to check the supply-current and bias-voltage levels during power-down mode. The proposed testbench uses standard UVM components as-is by encapsulating all the analog-specific contents in a fixture submodule. This fixture contains the DUT, generates analog stimuli, and measures amplitudes, using XMODEL primitives. By seamlessly integrating XMODEL’s ability to run fast and accurate analog simulations into a UVM testbench, an efficient SystemVerilog-based verification with SPICE-level accuracy is demonstrated.

Charles Dancak, Betasoft Consulting Inc

Conference Sponsors

Global Sponsors

  • 00Days Until Conference


Contact Us