Accelerating Error Handling Verification of Complex Systems: A Formal Approach

Error handling verification is one of the key phases in determining reliability of any embedded system. It involves verifying that the system correctly detects and gracefully reports various errors. Failure to report an error may expose security vulnerabilities. Due to the technology advancement in recent years, the complexity of embedded systems has increased, resulting in a greater number of error scenarios. This has made the task of error handling verification even more challenging. In this paper we will demonstrate how leveraging Formal Property Verification can address these challenges using our work on error handling verification of a lossless hardware Decompression IP.

Bhushan Parikh, Intel Corporation
Peter Graniello, Intel Corporation
Neha Rajendra, Intel Corporation