Oral/Lecture

Advanced Functional Verification for Automotive System on a Chip

Rapidly growing automotive semiconductor industry and the market requirements for advanced driver assistance system (ADAS) are leading a more complex and larger size automotive system on a chip (SoC) development. This paper studies on system level functional verification for automotive SoC. Specifically, it explains the automotive features that impose huge challenges on system level verification in terms of completeness and efficiency, and presents advanced verification approaches to solve these challenges. Firstly, complex power scheme in the automotive SoC is discussed as verification completeness challenge and the following approaches are provided as a solution: i) automatic coverage generation based on UPF, specification of power intents; ii) extension of the functional coverage with system control events; iii) assertion based low-power feature debugging methods. These approaches enhance metric driven low-power design verification and unveil undetected design bugs. Identified issues through proposed approaches are summarized in this paper so that it could be of practical help. Secondly, for self-diagnosis features that guarantee high system reliability of automotive SoC, limitations of existing simulation approaches when running usage scenarios are explained in terms of verification efficiency challenges. To deal with these challenges, new testbench architecture and test platform for efficient use of emulators are proposed. The proposed platform significantly reduces the TAT, thus confirming that tests difficult to validate earlier, can now be validated at the pre-silicon phase.

Jaein Hong, Samsung Electronics
Jieun Jeong, Samsung Electronics
Namyoung Kim, Samsung Electronics
Hongkyu Kim, Samsung Electronics
Sungcheol Park, Samsung Electronics
Sangjun Mun, Cadence Design Systems