Writing compact yet accurate System Verilog Assertions (SVA), to validate the behavior of a design is a difficult task to achieve , and often the actual written SVA deviates from the intended assertion/check, leading to missed design bugs or a lower functional coverage. This paper aims at solving such a problem of writing sophisticated SVA through machine learning by creating a pipeline or connectivity to understand the user’s natural language description of assertions and generate SVA, and vice-versa and thus bridging the gap for verification engineers who do not have prior knowledge of writing SVAs.