RISC-V becomes a hotspot in recent years, and some of the applications require high performance data access. In order to satisfy this, a lot of tricky logic is created in cache design, and cache verification has become a challenging task. In this paper, we present a flexible and extendable cache verification model which supports multi-thread and multi-core structure. The cache model will be introduced in two perspectives: The basic structure to fulfill cache’s data check, then extra ‘location’ information for more precise verification. We named the model as CAMEL (CAche ModEL) in short, as the model’s characteristic is just like camel’s two humps. Our goal is to make cache verification more general and flexible.