Runtime-configuration and operation of design IP is increasingly dependent on firmware. However, firmware for those IPs is often created too late, and in an unsuitable form, to be helpful in SoC-bringup tests. This presents an obstacle to creating SoC integration tests, and often results in late discovery of hardware/software interaction issues. This paper proposes an Accellera Portable Test and Stimulus (PSS) -enabled flow for co-developing and co-verifying design IP and firmware.