Confidently Sign-off any Low-Power Designs without Consequences

Successful verification of low-power designs has always been a challenge in the industry. The IEEE 1801 (UPF) standard introduces low-power modeling concepts into today’s complex designs. Different empirical studies shows that 40% or more of engineering time-effort is typically spent only on debug for any design verification project. For low-power design and verification, these debug challenges are further complicated, resource and time consuming as a consequences of complicated power management architectures and instrumentations implication on actual design. In this paper, we will provide an in-depth analysis of various low-power design issues that are faced daily basis. By taking relevant examples and case studies we will demonstrate how these issues can be either avoided or solved during RTL bring up phase.

Madhur Bhargava, Siemens EDA
Jitesh Bonshal, Siemens EDA
Progyna Khondkar, Siemens EDA