Poster

Emulation based Power and Performance Workloads on ML NPUs

As the design size and complexity of Modern SoCs are increasing, Power Verification has become extremely popular. It is important to keep power numbers under limits and this can be achieved by performing Power Calculations from the early stages of design cycle. Software simulators were used for this purpose, but for compute intense Power calculations, they slow down and can only run a few hundreds of thousands of cycles. Hence, Hardware Emulators are used for this purpose. In Emulators, verification is done on Hardware, hence they achieve much faster speeds than Simulators. In this paper, we will discuss about how the ML design was migrated from Simulation to Emulation platform and how Power Verification and Functional Verification were done on the design.

Pragati Mishra, Arm Ltd
Ritu Suresh, Arm Ltd
Issac Zacharia, Arm Ltd
Jitendra Aggarwal, Arm Ltd