Oral/Lecture

Flattening the UVM Learning Curve: Automated solutions for DSP filter Verification

By their nature, DSP filters are computationally intensive, predominantly structured as data paths with relatively simple control paths. Algorithm developers often develop filters using MATLAB, with hardware engineers developing RTL to implement the MATLAB specification. Traditionally, the verification of filters at unit level has been limited, with the RTL designer developing a simple testbench comparing RTL outputs against pre-generated MATLAB model outputs. That approach is now changing because complexity of control paths is increasing, algorithms are being modified frequently to conform with evolving standards and optimization is being done to minimize power consumption. These developments drive the need for more comprehensive verification methods. When considered as a standalone testbench, the DSP filter testbench is still quite small, but the number of such benches in a project is quite high. So, while we see the obvious benefits of implementing our testbenches in UVM, both the size and the number of testbenches make it prohibitive. This led us to explore “lite-UVM” testbenches with a high degree of automation. Our goal was to utilize the benefits of UVM based verification, but with minimal bring up efforts. In the paper, we document various solutions we explored to develop more robust verification spanning from homebrewed solutions through off-the-shelf industry tools. The intended audience for this presentation is DV and Design engineers looking for a light UVM framework that verifies DSP filters with complex data paths, but simpler control logic. We have classified this abstract into three parts – motivation, strategies, and conclusion.

Avinash Lakshminarayana, Silicon Laboratories, Inc.
Eric Jackowski, Silicon Laboratories, Inc.
Eric Cigan, MathWorks
Mark Lin, MathWorks