Oral/Lecture

Hierarchical UPF: Uniform UPF across FE & SD

Power intent specification of a System-on-Chip (SoC) using IEEE 1801 Unified Power Format (UPF) is a complicated task and requires coordinated efforts from RTL, validation, and SD (Structural Design) teams. Ideally, same set of UPFs (hierarchical UPFs) should be consumed across the different SoC domains, however, due to technological limitations in SD tools and flows, this was not done till now. Tools/flows/Methodologies used in past projects dictates SD uses merged UPFs, which requires 70% extra efforts for its generation, and about 2 months for the initial bring-ups with multiple configurations and manual hacks needed in Front End (FE). This also leads to scenario where verification is done on hierarchical UPF whereas execution is done on merged UPF; and the process of validating merged UPF equivalencies with the hierarchical UPFs is cumbersome and never full-proof, resulting in higher TAT (turn-around-time) and possible silicon escapes. But with advancement of tools, industry is now going forward with adopting the hierarchical UPFs for all the tools and flows, while most projects in Intel are still using different UPFs in FE and SD. In this paper we describe the Proof of Concepts (POC) and deployment done for using hierarchical UPFs in SD, advantages and recommendations/guidelines for its seamless consumptions. This empowered the graphics SoC team to adopt hierarchical UPFs for their current SoC also allowing them to consume the 3rd party IP UPFs directly after the integration, which is the right thing to do and was not possible earlier; and in turn reducing the manual work required for generating and validating the merged UPFs.

Dipankar Narendra Arya, Intel
Balaji Vishwanath Krishnamurthy, Intel
Aditi Nigam, Intel Tahir Ali, Intel