A major issue with emulation today is the inability to run randomized functional verification testbenches without a performance-degrading simulator integrated “on-the-side.” This workshop will demonstrate a method to execute randomized testbenches directly on the emulator, allowing for the high-performance functional verification of large blocks, sub-systems, and full SoCs.   Combined with the use of system-level encapsulated test IP and coverage-driven test synthesis, the workshop will provide participants with methods to fully test large blocks and SoCs in a manner that will uncover complex corner-cases not found with real-world test workloads. Such a solution allows companies to leverage their considerable investment in these devices more fully by extending them into the simulation acceleration space.   The two major elements of modern verification processes today are:

• The functional verification of design blocks using regression simulation and SystemVerilog/UVM test content.
• SoC validation leveraging real world workloads and booting operating systems employing an emulator or prototyping mechanism.

  However, there is a desired middle ground between these two processes where randomized functional tests executed at emulation performance will uncover additional bugs.  Typical issues that could be targeted include:

• Design functionality no longer contained within a single block, and could involve firmware as well as hardware, requiring subsystem functional verification.
• SoC integrity, for example cache and system coherency, power domain operation, security, etc., can be fully explored.
• Corner-cases caused by functional errors or performance bottlenecks that are harder to discover at the SoC level.

  This workshop will demonstrate the use of test suite synthesis methods by which a large block, sub-system or SoC may be fully, functionally verified on an emulator using functional techniques akin to block verification, as follows:

• Running randomized, pre-compiled test content on an emulator without a performance degrading simulator on the side executing the testbench.
• Leveraging pre-defined infrastructure validation test content IP or configurable apps to verify common SoC issues, such as cache coherency.
• Synthesizing test content that explores the relevant SoC state-space to track corner cases without every case having to be pre-determined.
• SoC coverage closure prior to the availability of the RTL blocks.

  Participants will learn proven, practical methods by which complex blocks, SoCs and sub-systems may be verified within ever-constrained schedules to a high degree of quality.