The development of secure and safe systems is of paramount importance in this age of vertically integrated electronic systems. The dependability of a system reflects the user’s degree of trust in that system. It reflects the extent of the user’s confidence that it will operate as users expect and that it will not ‘fail’ in normal use. Dependability covers the related systems attributes of reliability, availability, and security. Security weaknesses in the SoC hardware can lead to vulnerabilities that may be exploited later on by malicious intent in software or hardware. These challenging problems must be addressed pre-silicon and require rigorous methodology combined with technology to provide increased security assurance. Safety assurance requires a full product life cycle approach and is also tightly linked with security and lack of one, jeopardizes the other. In this tutorial, leading-edge SoC companies and Synopsys experts will discuss the safety and security solution for a hardware development lifecycle to achieve pre-silicon signoff.  Users will also learn the recommended methodology and best practices to address common weakness enumerations (CWE) and add counter measures to build threat and fault resilient designs. Additionally, the panel will discuss the challenges, new trends and requirements in next generation verification solutions for both ASIC and FPGA based designs. Target audience: RTL designers, Verification engineers, Project Leads and Managers.