In the Intel’s IOTG SoC Design, it is often a challenge to signoff gate level CDC or RDC verification because of the lack of IP/Subsystem hierarchal collaterals, lack of clock-reset architectural understanding in back-end domain, waiver importing issues, strict schedule pressure etc. However, with the advent of complex clock-reset architecture and due to the increase in reset signaling complexity with the emergence of multiple reset domains, gate level clock and reset domain crossing verification becomes an absolute need to ensure glitch free reset assertions during various power states. Therefore, there is a tangible need to define a methodology to ensure all the CDC or RDC issues post low power cell insertions, scan insertion and synthesis optimization are left-shifted in the Front-End CDC or RDC. This paper details about complex gate level CDC or RDC challenges in the IOTG SoC design and proposed few simple techniques in the front-end verification to address issues which are mainly related to implementation flows.