Machine Learning Based Verification Planning Methodology Using Design and Verification Data

As complexity and integration of SOC continue to increase, its development time increases significantly and the verification time does increase even more dramatically. In a typical verification process, a large number of directed or randomized simulation test cases are generated and run as a regression form. In a full chip verification environment, this regression takes significant amount of time to be completed and could be a critical path in a project schedule. In this paper, we discuss the methodology to efficiently manage the regression and reduce its run time. We classify test cases in regression by using various Machine Learning algorithms and correlate with the amount of design changes and previously failed simulation results. During this process, we are able to predict failing test cases in the early regression stage otherwise could find them in the later regression stage. It gives an additional debugging time and eventually help us to reduce total regression time. The proposed methodology is being applied to the latest mobile SOC projects.

Hanna Jang, Samsung
Seonghee Yim, Samgsung
Sunchang Choi, Samgsung
Seonil Brian Choi, Samgsung