Sponsored Tutorial

ML-Driven Verification: A Step Function in Productivity and Throughput

Cadence Design Systems
Verification productivity has historically been largely dependent on performance tooling, and engineering ingenuity in driving these tools. The entire verification loop from test content composition, execution, debug and coverage management features engineers manually devising test programs and analyzing the results.   Verification continues to evolve as block-level functional complexity increases and SoC verification becomes more relevant. Engineering teams must verify SoC infrastructure and device integrity as well as IP functionality. The complexity of 5G, Autonomous Driving, Quantum Computing and other applications shows no sign of decreasing.  Verification methodologies continue to progress to meet these challenges. Engineers need some help to contain the verification explosion driven by this expansion.   Machine Learning (ML) is proving itself a powerful weapon across many facets of engineering where increased complexity spills over the bounds of the human mind. Semiconductor verification clearly falls into this realm as tasks such as debug, test composition and coverage management require super-human intelligence just to perceive the problem. ML can be a vital aid to engineers struggling with these challenges in ever decreasing schedules and pressing quality demands.   This workshop will guide participants through the myriad of emerging ML applications within various verification tools, demonstrating how this new technology may make their everyday efforts more effective. ML applications to be considered will include:  
  • Simulation regression performance and efficiency. This includes regression compression, multi-core optimization, coverage closure through UNR, etc.
 
  • Proof engine selection and application in the use of formal methods, to maximize the capacity and convergence of this powerful tool.
 
  • Improved efficiency and automation of the regression triage and analysis flow, accelerating both the identification and categorization of bugs, as well as the debug and re-verify loop.
  Participants in this workshop will be provided a perspective on how to employ these new techniques on next generation verification environments, as they continue to drive towards first time silicon success. Cadence-logo-website

Matt Graham, vManager Product Engineering Group Director, Cadence

matt_graham

Amit Dua, Sr. Xcelium Product Engineering Group Director, Cadence

amit_dua

Daniel Hansson, Principal ML Software Engineer, Cadence

daniel_hansson (1)