Formal Verification is a well-established technique for efficient and exhaustive verification complex designs in pre-silicon phase. Today, it is also proving out to be highly effective in assisting post-silicon debug as well as building confidence in bug fixes that goes into re-spins. Enabling formal verification in post-silicon phase poses different challenges than in pre-silicon phase. In this paper, we present a stepwise guide to apply formal verification in post-silicon phase for reproducing bugs, validating the bug fixes, building a solution capable to uncover remaining vulnerabilities lurking in other parts of design, finally yielding high confidence in design. A case study is presented to illustrate the effectiveness of our methodology in successful tape-out.