During Pre-Silicon validation, pure SoC RTL simulation/emulation platform is highly used to validate synthetic and bare metal test content using synthetic BIOS. Synthetic BIOS is a bare minimum version of production BIOS which is used on Pre-Si platforms. Since these platforms don’t easily support deployment of full stack software, majority of the validation doesn’t involve production BIOS, OS, full stack drivers and real workloads for accelerator IP’s like 5G, AI. Enabling Pre-Si platform with the capability to validate critical SW collaterals and SW use cases will help to unearth potential bugs. These bugs, if found directly during Post-Silicon validation, requires enormous amount of debug effort, and may even harm the silicon quality. Exhaustive Pre-Si validation of workloads provides better performance validation and reduces the risk of performance bugs on the silicon. This approach saves debug time on silicon and occasionally avoids even re-spinning cost. Hence, it becomes essential to exhaustively validate SW collaterals and SW use cases at Pre-Si stage itself to shift left the validation, improve validation coverage matrix, and target high quality A0 PRQ. To achieve this goal, we created custom Hybrid SLE platform, which combines cores from Simics and rest of SoC from RTL Emulation. Simics is a system simulator, which will provide the required acceleration to execute BIOS, CentOS, and SW content. Whereas the RTL provides the apt platform for Pre-Si validation. In this paper we present the methodology to perform validation of SW collaterals and SW use cases using custom Hybrid System Level Emulation Pre-Silicon SoC platform. SW collaterals include production BIOS, OS, FW, Drivers and production Fuses. SW use cases include platform reset, power management and SW application for Core and Accelerator IP workloads. This validation at Pre-Si helps to achieve high quality for Intel products, target A0 PRQ and reduce Time to Market.