IEEE 1801 UPF format comes with a limitation that it doesn’t entirely support decoupling of front and backend power intent files and as many SoC projects in Intel are marching towards ASIC products on different process technologies, it becomes more important for designers to code power intent with the process agnostic approach. Therefore, IEEE 1801-2015 UPF (UPF3.1) has come up with a methodology called Successive refinement that supports Incremental specification. This methodology enables incremental design and verification of the power management architecture, and it is specifically designed to support specification of power management requirements for IP components used in a low power design. This incremental flow accelerates design and verification of the power management architecture using partition methodology wherein the power intent is partitioned into constraints, configuration, and implementation. In this paper, we will present the new methodology Successive refinement implemented for IOTG-SOC in which power intent is specified in a technology independent manner and verified abstractly before implementation.