SystemC Virtual Prototype: Ride the earliest train for Time-To-Market !
The growing interest in multiprocessor system-on-chip designs has introduced an equally complex software development and validation challenge. System design is increasingly being performed at higher levels of abstraction to deal with variety of issues. Early Software development has now become a key System level design initiative, so our focus must shift from “Are we building the product right?” to “Are we building the right product?”. Virtual Prototyping is a novel method to meet the expectation of first silicon success and tight schedules for aggressive time-to-market windows by utilizing the time between defining system design specification till the actual hardware is designed.
Shweta Saxena, Analog Devices Inc
Mahantesh Danagouda, Analog Devices Inc