For silicon validation, it is critical to have a test framework which can seamlessly scale from IP level to subsystem level to SoC level test cases. In contrast to the mature flows & methodologies ecosystem that exists for pre-silicon verification, post-silicon validation is still heavily dependent on ad-hoc test development and pointed solutions. This makes it very difficult to develop a test suite which can systematically scale and be re-used across similar/derivate projects. Our proposed methodology using PSS-HSI sequences enables Pre-Silicon and Post-Silicon teams to use the same test content, and collaborate on developing HSI sequences, while eliminating the duplication of effort needed to create driver sequences for SV-UVM and core-based environments. Since its initial release in July 2018, the Portable Test and Stimulus Standard (PSS) has provided a specification to create a single representation of stimulus and test scenarios usable by a variety of users across many levels of integration under different configurations. This representation facilitates the generation of diverse implementations of a scenario that run on a variety of execution platforms, including, but not necessarily limited to, simulation, emulation, FPGA prototyping, and post-silicon. The PSS HSI layer enables users to write a single implementation of device driver logic in portable terms: – Abstracts the mechanics of lower-level register access. – HSI provides much more than simple register abstraction, it provides a representation of memory, registers, interrupts, synchronization etc, enabling efficient way to implement driver logic. – HSI sequences can be mapped to both UVM-agent based environments and embedded core-based environments. Combining the constraint-randomization and code-generation features of PSS tool along with HSI provides a powerful way for test-case automation.