What Does the Sequence Say? Powering Productivity with Polymorphism

In a SystemVerilog UVM testbench a UVM sequence is much like a program or a function call or a test. Writing interesting sequences can help with productivity and coverage closure. On one hand a sequence is simply a list of instructions, but on the other hand how those instructions are built or how they are used with other instructions can improve the test. This paper will demonstrate such improvements.

Rich Edelman, Siemens EDA