<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="/__sitemap__/style.xsl"?>
<urlset xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:video="http://www.google.com/schemas/sitemap-video/1.1" xmlns:xhtml="http://www.w3.org/1999/xhtml" xmlns:image="http://www.google.com/schemas/sitemap-image/1.1" xmlns:news="http://www.google.com/schemas/sitemap-news/0.9" xsi:schemaLocation="http://www.sitemaps.org/schemas/sitemap/0.9 http://www.sitemaps.org/schemas/sitemap/0.9/sitemap.xsd http://www.google.com/schemas/sitemap-image/1.1 http://www.google.com/schemas/sitemap-image/1.1/sitemap-image.xsd" xmlns="http://www.sitemaps.org/schemas/sitemap/0.9">
    <url>
        <loc>https://dvcon.org/</loc>
        <lastmod>2026-01-23T13:35:19Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/2025-accellera-sponsored-lunch</loc>
        <lastmod>2025-01-27T00:49:26Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/accelerating-design-verification-with-ai-agents</loc>
        <lastmod>2025-01-22T21:33:02Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/accelerating-functional-verification-with-machine-learning</loc>
        <lastmod>2025-01-22T21:31:28Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/accellera-sponsored-lunch-accellera-luncheon-focused-on-federated-simulation</loc>
        <lastmod>2024-02-08T20:08:23Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/beyond-integers-and-floating-point-designing-and-verifying-with-alternate-number-representations-0</loc>
        <lastmod>2025-01-22T21:37:13Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/cdc-rdc-interchange-format-standard</loc>
        <lastmod>2025-01-22T21:38:19Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/complex-verification-example-risc-v-mmu-verification-of-virtualization-and-hypervisor-operation-for-cpu-and-soc-platforms</loc>
        <lastmod>2025-01-22T21:35:20Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/comprehensive-glitch-signoff-learnings-and-experiences-from-industry-use-cases</loc>
        <lastmod>2025-01-22T21:38:00Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/emulation-driven-power-estimation-for-real-world-application</loc>
        <lastmod>2025-01-22T21:33:26Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/introduction-of-ieee-1801-2024-upf-4-0-improvements-for-the-specification-and-verification-of-low-power-intent</loc>
        <lastmod>2025-01-22T21:31:58Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/ip-xact-workshop-at-dvcon-us-2025</loc>
        <lastmod>2025-01-22T21:37:35Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/modernizing-the-hardware-software-interface-life-beyond-spreadsheets-how-to-bring-your-soc-register-design-into-the-21st-century</loc>
        <lastmod>2025-01-22T21:29:49Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/moving-application-level-power-optimization-to-pre-silicon-with-advanced-hybrid-emulation-and-power-exploration-technologies</loc>
        <lastmod>2025-01-22T21:34:34Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/moving-forward-with-ieee-1800-2-uvm-practical-insights-and-the-benefits-of-migration</loc>
        <lastmod>2025-01-22T21:32:36Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/next-gen-verification-technologies-for-processor-based-systems</loc>
        <lastmod>2025-01-22T21:36:40Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/poster-session</loc>
        <lastmod>2025-01-27T13:30:28Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/power-dynamics-shaping-the-future-of-the-data-centric-era</loc>
        <lastmod>2025-01-22T21:35:50Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/press-release-august-1-2023</loc>
        <lastmod>2023-12-19T22:00:36Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/press-release-february-8-2023-2</loc>
        <lastmod>2023-12-19T22:00:14Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/press-release-january-21-2025</loc>
        <lastmod>2025-01-17T19:31:06Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/press-release-june-27-2023</loc>
        <lastmod>2023-12-19T22:00:21Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/press-release-march-8-2023</loc>
        <lastmod>2023-12-19T21:55:24Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/press-release-march-20-2024</loc>
        <lastmod>2024-03-18T17:29:25Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/press-release-may-7-2024</loc>
        <lastmod>2024-05-06T18:44:27Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/prospectus</loc>
        <lastmod>2026-01-20T17:03:38Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/pss-case-studies-in-real-life-projects</loc>
        <lastmod>2025-01-22T21:33:46Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/pss-comes-of-age-runtime-behavioral-coverage-methodology-and-more</loc>
        <lastmod>2025-01-22T21:34:57Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/registration</loc>
        <lastmod>2026-01-30T15:05:24Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-1-low-power-upf</loc>
        <lastmod>2025-01-24T17:26:06Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-2-functional-safety</loc>
        <lastmod>2025-01-23T01:11:29Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-3-ai-ml-in-verification</loc>
        <lastmod>2025-01-23T01:12:01Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-4-portable-stimulus</loc>
        <lastmod>2025-01-23T01:14:58Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-5-ai-ml-coverage-closure</loc>
        <lastmod>2025-01-23T01:15:29Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-6-regression-management</loc>
        <lastmod>2025-01-23T01:15:56Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-7-formal-verification</loc>
        <lastmod>2025-01-23T01:16:20Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-8-uvm-in-practice</loc>
        <lastmod>2025-01-23T01:16:51Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-9-coverage-modeling</loc>
        <lastmod>2025-01-27T21:28:02Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-10-verification-ip</loc>
        <lastmod>2025-01-23T01:17:50Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-11-testbench-generation</loc>
        <lastmod>2025-01-23T01:18:16Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/session-12-analog-digital-mixed-signal</loc>
        <lastmod>2025-01-23T01:18:46Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/siemens-sponsored-lunch-how-your-d-v-challenges-drive-our-innovation-insights-from-the-top</loc>
        <lastmod>2024-02-13T17:40:27Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/sponsor-exhibitor-resources</loc>
        <lastmod>2026-02-10T20:26:12Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/step-function-leaps-in-rtl-functional-verification-powered-by-ai-ml-innovations</loc>
        <lastmod>2025-01-22T21:34:12Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/synopsys-sponsored-lunch-overcoming-the-challenges-of-multi-die-system-verification</loc>
        <lastmod>2024-01-31T13:13:55Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-1-functional-coverage-closure</loc>
        <lastmod>2024-02-12T20:53:12Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-2-ai-ml-in-verification</loc>
        <lastmod>2024-02-01T22:26:43Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-3-formal-verification-use-cases</loc>
        <lastmod>2024-02-01T22:27:30Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-4-uvm-testbenches</loc>
        <lastmod>2024-02-01T22:29:01Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-5-functional-safety-and-verification</loc>
        <lastmod>2024-02-15T16:36:31Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-6-riscv-design-verification</loc>
        <lastmod>2024-02-01T22:30:29Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-7-requirements-definition-and-traceability</loc>
        <lastmod>2024-02-28T13:22:55Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-8-mixed-signal-with-uvm-verification</loc>
        <lastmod>2024-02-01T22:32:27Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-9-systemverilog-verification-techniques</loc>
        <lastmod>2024-02-01T22:33:03Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-10-requirements-definition-and-traceability</loc>
        <lastmod>2024-02-01T22:34:34Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-11-formal-liveness-and-use-cases</loc>
        <lastmod>2024-02-01T22:35:10Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-12-analog-modeling-in-systemverilog</loc>
        <lastmod>2024-02-01T22:35:43Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/technical-session-posters</loc>
        <lastmod>2024-02-15T16:35:53Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/tutorial-portable-stimulus</loc>
        <lastmod>2024-02-05T17:44:59Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/venue-accommodations</loc>
        <lastmod>2026-02-18T19:37:58Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/visiting-san-jose</loc>
        <lastmod>2024-02-21T01:38:04Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/workshop-automating-the-integration-workflow-with-ip-centric-design</loc>
        <lastmod>2024-02-02T20:16:50Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/workshop-functional-safety</loc>
        <lastmod>2024-01-18T20:13:04Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/workshop-introduction-to-ip-xact</loc>
        <lastmod>2024-02-19T20:34:00Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/workshop-uvm</loc>
        <lastmod>2024-02-26T21:08:55Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/workshop-uvm-a-practical-guide-to-sa-edi-methodology</loc>
        <lastmod>2024-02-29T17:48:53Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/about/sponsor-and-privacy-policy</loc>
        <lastmod>2023-12-06T20:14:54Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/about/steering-committee</loc>
        <lastmod>2026-01-15T15:50:01Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/affiliates/marketing-toolkit</loc>
        <lastmod>2024-01-08T19:21:36Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/hotel-travel/avoid-hotel-fraud</loc>
        <lastmod>2024-04-26T22:55:15Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2025-keynote-presentations</loc>
        <lastmod>2025-01-10T13:49:20Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2025-program-grid</loc>
        <lastmod>2025-02-20T20:51:52Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2025-technical-sessions</loc>
        <lastmod>2025-01-27T21:27:28Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/submission-instructions/call-for-extended-abstracts</loc>
        <lastmod>2025-12-17T23:36:31Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/submission-instructions/call-for-panels</loc>
        <lastmod>2025-05-13T18:49:06Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/submission-instructions/important-dates</loc>
        <lastmod>2023-12-06T19:34:20Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/submission-instructions/speaker-resources-and-guidelines</loc>
        <lastmod>2026-01-20T17:07:46Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/submission-instructions/tutorial-workshop-submissions</loc>
        <lastmod>2025-12-17T23:37:01Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/media/news/press-release-february-15-2024</loc>
        <lastmod>2024-02-14T17:02:07Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/media/news/press-release-january-11-2024</loc>
        <lastmod>2024-01-11T19:44:53Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/media/photos/2024-photos</loc>
        <lastmod>2024-03-12T21:08:56Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/2024-program-grid</loc>
        <lastmod>2024-03-04T20:08:16Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/2024-stuart-sutherland-best-paper-best-poster-award-recipients</loc>
        <lastmod>2024-03-07T19:07:59Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/keynote-presentation</loc>
        <lastmod>2024-12-16T21:28:32Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/panel-when-will-we-be-able-to-say-eda-gpt-verify-my-asic</loc>
        <lastmod>2024-01-17T13:38:52Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/tutorial-data-driven-design-verification-validation-and-signoff-case-studies-of-risc-v-socs</loc>
        <lastmod>2024-01-15T17:56:26Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/tutorial-streamlining-low-power-verification-from-upf-to-signoff</loc>
        <lastmod>2024-01-15T17:56:17Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/tutorial-usf-based-fmeda-driven-functional-safety-verification</loc>
        <lastmod>2024-01-15T17:56:07Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-advanced-ucie-based-chiplets-verification-from-ip-to-soc</loc>
        <lastmod>2024-01-15T17:55:53Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-automatic-generation-of-device-driver-and-programmers-reference-manual-from-pss</loc>
        <lastmod>2024-01-15T17:55:42Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-emulation-moves-into-4-state-logic-and-real-number-modeling</loc>
        <lastmod>2024-01-15T17:55:32Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-expanding-role-of-static-signoff-in-verification-coverage</loc>
        <lastmod>2024-01-15T17:55:22Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-fpga-prototyping-for-large-multi-die-multi-core-designs</loc>
        <lastmod>2024-01-15T17:55:11Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-hierarchical-cdc-and-rdc-closure-with-standard-abstract-models</loc>
        <lastmod>2024-02-19T23:16:16Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-introduction-to-ip-xact</loc>
        <lastmod>2024-01-15T17:54:49Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-RISC-VCore</loc>
        <lastmod>2024-01-15T17:54:38Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-systemc-model-code-generation-using-large-language-models</loc>
        <lastmod>2024-01-15T17:54:28Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2024/workshop-your-soc-your-topology</loc>
        <lastmod>2024-01-15T17:54:16Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2025/2025-tutorials-workshops</loc>
        <lastmod>2025-01-22T20:56:00Z</lastmod>
    </url>
    <url>
        <loc>https://dvcon.org/program/2026/stuart-sutherland-best-paper-best-poster-award-voting</loc>
        <lastmod>2026-02-20T19:47:10Z</lastmod>
    </url>
</urlset>
<!-- XML Sitemap generated by @nuxtjs/sitemap v7.0.1 at 2026-04-03T17:29:31.260Z -->