In this tutorial, you will learn how to write a UVM testbench for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes for building reusable and scalable testbenches for digital systems, and we will show that it can be extended to verifying analog circuits simply by using a well-defined fixture module encapsulating the device-under-test (DUT) and its AMS instrumentations described with XMODEL primitives. Through a series of hands-on lab exercises using a digitally-programmable audio bandpass filter as an example, you will learn how to write a UVM testbench that measures the filter’s transfer gains at randomly-chosen frequencies and collects the results in a scoreboard.
The tutorial is organized in two parts. The first part introduces XMODEL as a way of modeling and simulating analog circuits in SystemVerilog. The lab exercises will show how to auto-extract a SystemVerilog model from the analog filter circuit and build a SystemVerilog testbench measuring its response to a sinusoidal input using XMODEL primitives. By the end of the first part, you will have your fixture module enclosing the analog DUT and its instrumentations ready.
The second part starts with an intuitive overview of UVM and shows how to put the sequencer, driver, monitor, and scoreboard components around the fixture module to build a UVM testbench. The lab exercises will guide you how to write a sequencer generating a sequence of random frequencies, a driver sending the stimulus data to the fixture module, a monitor receiving the measured responses from the fixture, and finally a scoreboard comparing the results against the SPICE simulation data. By the end of this second part, you will be running simulation with your own UVM testbench verifying the filter’s transfer gains at randomly-chosen frequencies.
No strong background is required either in analog circuits or digital verification. Each concept, feature, or technique is introduced in a step-by-step fashion and anyone with a basic knowledge of SystemVerilog is welcome to attend.
Jaeha Kim & Charles Dancak