Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Verification engineers use various criteria such as bug rates and coverage metrics or at least asymptotically converge toward target goals to determine when to signoff.
In this workshop, we present a new and differentiating AI-driven verification technology, known as Intelligent Coverage Optimization (ICO). The workshop will demonstrate how verification engineers can benefit from early adoption of ICO’s simple use model to accelerate coverage convergence in simulation, expose bugs early in the design cycle, reduce debug effort and improve verification turnaround time, thereby maximizing project resource utilization while reducing the verification schedule. ICO leverages modern artificial intelligence (AI) and machine learning (ML) technologies to help optimize coverage and stabilize the testbench. Through continuous feedback, the testbench is stabilized faster with each verification cycle and as more project experience is accumulated.
We will present real case studies showing how the entire verification process shifted left using ICO early in the cycle. Employing AI-driven verification techniques reduced the manual effort to write directed tests, helping find bugs faster, and required fewer regression iterations to reach the target metrics, saving several weeks of effort and up to 15% reduced peak demand of grid resources.
Maley Ganai, Will Chen, Srikanth Vadanaparthi