Processor core verification represents an array of complex challenges. With the advent of RISC-V, new issues have emerged, which add to this complexity. Whether you are a processor developer working on a RISC-V or other core, or an SoC integrator incorporating one of these new processors, the learning we will provide in this workshop will add to your arsenal of verification techniques.
Breker has been working with multiple RISC-V vendors and users. We have discovered that tests used to ensure the smooth integration of these processors into SoCs, both large and small, may also be applied to cores under development in unique ways to drive increased quality. For example, interrupt testing at the SoC level may also be applied to the core to ensure the smooth handling of the operational interrupt. Load Store mechanisms at the SoC level may be introduced at the core level to understand if the device can be tripped up. Will the RISC-V memory protection be enough to ensure security at the SoC level? Of course for multiple core or application devices, full system coherency becomes a critical component.
What are the algorithms that may be effectively used to provide these tests? How do you ensure full coverage of multi-faceted tests? How can you torture test the core and SoC to tease out complex, hard to predict corner cases in which might lurk a bug or an operational bottleneck? All of these questions will be answered during this workshop.