With ever-increasing chip design complexity, including chips for domain-specific applications, the role of on-chip and off-chip protocols have increased drastically. Protocol versions are evolving very rapidly to meet application needs for bandwidth, latency, and coverage. Verifying these protocols for behavior, performance, and power in actual application payloads and usage scenarios is absolutely necessary.
In this workshop, we will discuss how protocol verification is becoming more and more challenging as designs evolve from IP blocks to multi-die system setups and why IP verification is no longer enough. An end-to-end protocol is essential to validate protocol behavior and fulfill verification requirements for IP through system designs. We will walk through uses cases for when to apply virtual models, speed adapters, virtual transactors, and protocol interface cards to exercise interfaces from IP to systems. We will also discuss various power, performance, and pre-to-post silicon continuity use cases that are enabled with an end-to-end protocol verification solution.