Sponsored Workshop: Pushbutton Complete IP Generation

In IP/SoC design development, after capturing the register specification, the designers work on creating a synthesizable hardware application logic layer for their intended design functionality using the addressable hardware registers.

In this workshop, we plan show how to automatically create that synthesizable application logic layer along with its RAL and AI based uvm tests for completely automating the development at the lower levels of the layered SoC/IP design development.

Abhishek Chunhan

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