Growth in complexity of ICs, particularly SoCs, continues at a pace that will cause verification requirements to out run engineering capacity, compute capacity and tool performance. A new generation of EDA tools must emerge, leveraging big data and deploying AI across multiple runs of multiple engines to enable a dramatic increase in overall productivity.
The recently announce Cadence Verisium AI-Driven Verification platform is a suite of applications that represents just such a generational shift for verification campaigns. The Verisium platform, built on the Cadence Joint Enterprise Data and AI (JedAI) Platform provides capabilities that truly reduce silicon bugs and accelerates time to market.
In this session, we will highlight how a shift to multi-run, multi-engine solutions can address the continued increase in the effort required to close verification. The application of big data and AI to the verification problem will also be introduced, with particular emphasis on its application to debug. A number of the apps from the Verisium Platform will be reviewed, along with some insight into their leveraging of multiple engines (Japser Formal, Xcelium Logic Simulation) and their connections to multiple data sources (waveforms, RTL, coverage and revision control data).
Finally, we’ll review some of the results that users of such technologies are experiencing, and discuss some of the future potential of these technologies.