DVCon U.S. 2019 Welcome Message from the Chair

Welcome to DVCon U.S. 2019! It is truly a privilege to present the DVCon conference and exhibition that will provide a tremendous opportunity for attendees to survey and learn the latest in design and verification technologies, methodologies, and tools from the best in the industry.

Now in its 31st year, DVCon has established itself over the past three decades as the must-attend industry-focused conference for practicing design and verification engineers, EDA developers, and design managers. We are very proud of our long-standing tradition of providing a very technical forum where colleagues can share practical knowledge. It is an opportunity to discuss challenges and solutions that can be beneficial in your current and upcoming projects, as electronic designs and verification complexities and challenges continue to grow at a rapid pace.

With a record number of submissions, the 2019 conference promises to provide another outstanding technical program this year. We received nearly 160 excellent submissions for papers, panels, tutorials, and short workshops from the best technical minds and organizations in the industry. The in-depth technical sessions and posters cover broad topic areas such as formal verification techniques and methodologies, verification strategies, applying the Portable Stimulus Standard and case studies, hybrid verification environments, UVM, power-aware design and verification, and analog/mixed-signal verification. Attendees will find each of these areas addressed at the conference’s sessions, panels, posters, tutorials, and short workshops with an emphasis on real-world solutions to engineers’ real-world problems. Our focus on the users of Accellera standard EDA languages, tools, and methodologies continues to be a DVCon 2019 hallmark. Attendees can expect to learn about both practical solutions to their pressing problems, and also receive a preview of the technologies that will affect them in the near future.

I am very pleased to present the work of the DVCon Steering Committee and Technical Program Committee members, who have all volunteered to put together an excellent 2019 program with the support of our conference management specialists, MP Associates.

Highlights of the conference include:

Accellera Day:On Monday our conference sponsor, Accellera Systems Initiative, kicks off DVCon U.S. with Accellera Day. We’ll have a full-morning tutorial offering tips and tricks on UVM presented by well-known industry guru Cliff Cummings, and a short workshop on functional coverage for SystemC in the afternoon. The first day will be a little different than in the past with the addition of five sponsored short workshops in the afternoon.

Keynote:We’re also looking forward to an interesting keynote to be given by Fram Akiki, Vice President, Electronics & Semiconductor Industry for Siemens PLM Software. This will be the first time Mr. Akiki has addressed the DVCon U.S. audience, and we’re thrilled to have him participate in our conference this year.

Technical papers and posters: My thanks to our Technical Program Chair, Tom Fitzpatrick, and Poster Chair, John Dickol, who have organized an excellent technical program with multiple sessions that include 39 papers and 25 posters. There are so many good choices that you will want to go through the program and review it thoroughly as you plan each day. Topic areas this year range from big data, UVM, and portable stimulus to RISC-V and machine learning. There is something for everyone in this broad, in-depth technical program. With so many interesting options, we look forward to your votes for the best paper and best poster awards.

Tutorials and Short Workshops: I appreciate the excellent effort by Vanessa Cooper, our Tutorial Chair, for putting together an outstanding selection of tutorials for Monday and Thursday as well as an expanded Short Workshop program. As a result of overwhelming interest in our short workshops that debuted last year, we have expanded the workshops from one to two days. The workshops are intended to give more organizations, mostly smaller companies, greater opportunity to participate in the program and give attendees more variety in shorter educational and learning sessions. We have eight sponsored short workshops in this year’s program, five on Monday and three on Thursday, with topics ranging from deep learning and formal verification, to how to use the new Portable Test and Stimulus Standard 1.0.

In addition to the opening tutorial covering UVM tips and tricks on Monday, on Thursday we will have three sponsored tutorials with topics covering the use of next-generation IC development practices to build and validate smarter, safer ICs; formal verification applications and recent advancements; and data-driven verification productivity improvements.

Panels: My thanks to our Panel Chair, Ambar Sarkar, who has organized two excellent panel sessions. The first panel is on deep learning and artificial intelligence and how these may or may not reshape the semiconductor industry. The second panel will focus on verification and compliance in the era of open ISA. For example, with the new, open-standard RISC-V ISA, the compliance situation is different. There is no single IP vendor, no single source, so compliance is an issue that must be addressed. Both panels will provide some interesting perspectives for attendees to consider and also provide an opportunity to ask their own thought-provoking questions.

Exhibits: The exhibition continues to be one of the most sought-after gathering spaces among attendees to talk with exhibitors to learn the latest information on their products, share new information among peers, and enjoy the evening receptions. As of this writing, the exhibit floor is nearly sold out. We have 22 exhibitors registered and expect a full house of over 30.

In response to feedback from our attendees, we’re ending the program a little earlier on Thursday to give travelers a better opportunity to catch their afternoon and evening flights home. We hope this is helpful as we don’t want attendees to have to miss out on an interesting topic or need to leave a presentation before it has ended.

My sincere thanks to our sponsor, Accellera Systems Initiative, as well as our outstanding Steering Committee members, Technical Program Committee members, and MP Associates staff who have worked very hard to put together a program that makes DVCon “the” conference for design and verification engineers.

I’d also like to extend my thanks to past DVCon U.S. Chairs, Dennis Brophy and Stan Krolikoski, who continue to provide me with great advice and support throughout this process.

I sincerely look forward to seeing you in February in San Jose, CA at DVCon U.S. 2019!

 

Aparna Dey DVCon U.S. 2019 General Chair