March 2-5, 2020

DoubleTree Hotel, San Jose, CA

DVCon U.S. 2020 Welcome Message from the Chair

I am pleased to welcome you to the DVCon U.S. 2020 conference and exhibition! This year, DVCon promises to provide the attendees with outstanding technical sessions and discussions on many hot topics, practical learning, networking and an opportunity to preview the latest industry design and verification tools and services from the best in the industry.  We are proud of continuing our tradition of providing an annual technical forum that serves the needs of the design and verification community, organized by dedicated volunteers from the community itself. 

Now in its 32nd year, DVCon U.S. has established itself as the must-attend industry and user-focused conference for practicing design and verification engineers, EDA developers and design managers, focusing on design and verification of electronic systems and integrated circuits. We are proud that this conference attracts wide participation from the industry from the smaller to the larger companies in the full program and exhibition. We are also pleased that the success of DVCon U.S. and its format has spawned successful local DVCon events worldwide in Europe, China and India to meet the local needs of these regions. 

Our 4-day program includes many key design and verification topics including Formal verification, Portable Stimulus, IP Security, Intelligent System Design, AI and ML-focused verification, 5G verification, UVM Strategies, Power-Aware Design and Hybrid Verification, among others. The event provides an opportunity to discuss challenges and solutions that can be beneficial in current and upcoming projects as electronic designs and verification complexities and challenges continue to increase exponentially. Attendees will find each of these areas addressed at the conference’s sessions, panels, posters, tutorials, and short workshops with an emphasis on solutions to engineers’ real-world problems.

We are pleased to offer an in-depth technical program this year. We received over 160 outstanding submissions for papers, panels, tutorials, and short workshops from the best technical minds and organizations in the industry. Our focus on the users of Accellera standard EDA languages, tools, and methodologies continues to be a DVCon 2020 hallmark. Attendees can expect to learn about both practical solutions to their pressing problems and preview the technologies that will affect them in the near future.

I am pleased to present the work of the DVCon Steering Committee and Technical Program Committee, who have put together an excellent 2020 program with the support of our conference management specialists, MP Associates.

Highlights of the conference include:

Accellera Day: On Monday, March 2, our conference sponsor, Accellera Systems Initiative, kicks off DVCon U.S. with Accellera Day. We’ll have a full-morning Accellera tutorial on Portable Stimulus and the standard’s latest version updates as well as 2 Accellera short workshops in the afternoon on SystemC case studies and the IP Security Assurance standard presented by Accellera standards working group members. We’ll also have 4 sponsored short workshops in the afternoon presented by design verification industry members covering topics such as Portable Stimulus deployment, SOC methodology, and UVM test bench.

Keynote: This year’s keynote, “Artificial Intelligence for Design Automation,” will be given by Dr. Anirudh Devgan, president of Cadence Design Systems, Inc. Dr. Devgan’s talk will review the latest trends in artificial intelligence and machine learning and their impact on the EDA industry. He will examine how deep learning will chart a path beyond current practices, moving toward intelligent system design for an AI-enabled future. 

Technical papers and posters: Technical Program Chair, Vanessa Cooper, and Poster Chair, John Dickols, have organized an excellent technical program on Tuesday and Wednesday with 13 sessions that include 42 papers and 23 posters. We are very grateful for the outstanding submissions and the work done by the technical program committee volunteers to review the submissions and encourage the community to keep submitting. There are so many good choices that you will want to go through the program and review it thoroughly as you plan each day. There is something for everyone in this broad, in-depth technical program. With so many interesting options, we look forward to your votes for the best paper and best poster awards after the last program session on Wednesday. 

Tutorials and Short Workshops: Ambar Sarkar, tutorial and short workshop chair, has put together an outstanding selection of tutorials and short workshops for Monday and Thursday. The short workshops are very popular and are intended to give more organizations, mostly smaller companies, greater opportunity to participate in the program and give attendees more variety in shorter educational and learning sessions. We have 8 sponsored short workshops in this year’s program—4 on Monday and 4 on Thursday—covering a wide variety of topics.

In addition to the opening Accellera tutorial on Portable Stimulus on Monday, we will have three sponsored tutorials on Thursday with topics covering: Deploying VCS on Cloud for faster time to market and higher quality verification; Design and Verification of an ML based SoC using a software-driven system design approach; and Next Generation Verification for the era of AI, ML and 5G. 

Panels: Tom Fitzpatrick, panel chair has organized two excellent panel sessions. The first panel, “New Chip Designs Create Tidal Wave of Change”, will address the need for a more thorough verification methodology as complexity converges with open source initiatives such as RISC-V. The second panel, “Predicting the Verification Flow of the Future”, will focus on what’s straining today’s verification environment and what might be needed to support future applications. Both panels will provide some interesting perspectives for attendees to consider and also provide an opportunity to ask their own thought-provoking questions.

Exhibits: The exhibition continues to be one of the most sought-after gathering spaces among attendees to talk with exhibitors to learn the latest information on their products, share new information among peers, and enjoy the evening networking receptions. As of this writing, the exhibit floor is nearly sold out.  We have a few spaces left, but expect a full house of more than 30 when the conference begins.  

My sincere thanks to our program sponsor, Accellera Systems Initiative, industry sponsors, steering committee volunteers, technical program committee volunteers, past chairs and MP associates staff who have worked hard to put together a program that makes DVCon “the” conference for design and verification engineers. 

I sincerely look forward to seeing you in March in San Jose, CA at DVCon U.S. 2020!

 

Aparna Dey DVCon U.S. 2020 General Chair