February 27 - March 2, 2017

DoubleTree Hotel, San Jose, CA

DVCon U.S. 2017 Welcome Message from the Chair

Welcome to DVCon U.S. 2017! It is hard to believe, but for almost 30 years, 29 to be precise, we have been gathering to explore advances in language-based design automation methodologies and electronic system verification techniques. We trust you will get a lot out of the 29th DVCon that you can apply to your daily design and verification activities.

The DVCon format is uniquely focused on the needs of electronic design and verification teams and to those in the electronic systems design automation industry who are focused on algorithmic advances, tool development and application of standards. This conference is more than just a conference, it is a community gathering that acts as an annual milestone in technology evolution and a means by which we can share best practices with each other and set the next technology goalposts as we are challenged by ever increasing design complexity.

Accellera Systems Initiative hosts the conference but the DVCon volunteers taking input from design and verification engineers around the world bring the conference to life. The volunteers are DVCon’s life blood. As General Chair, I have the honor and privilege to work with a dedicated team of volunteers. While you enjoy DVCon, feel free to connect with me and other conference volunteers if you would like to explore an active volunteer role as well. We are always looking for additional passionate individuals to join us.

DVCon is a fixture in our industry to explore the most advanced technologies to help design and verify the most complex chips. Those collaborating with me as your General Chair include several of the past DVCon chairs, particularly Yatin Trivedi and Stan Krolikoski who are full of insights and advice. I extend my gratitude for their past service and willingness to help DVCon evolve by offering their continued counsel. If you don’t recall, Yatin and Stan are the last two immediate DVCon U.S. General Chairs. They have been very involved to help make DVCon a global event where local design verticals and technologies focused in certain geographies give each DVCon their own flavor.

How do we bring DVCon to life? The Program Chair, Tom Fitzpatrick, plays a pivotal role to create a compelling technical program for you. He has a large team of reviewers that have culled the paper submissions to create this great, comprehensive program. We offer a balance to the technical sessions with training, tutorials, poster sessions, panels and more. DVCon starts with Monday “Accellera Day” tutorials. Accellera working groups use the Monday tutorials to highlight current and emerging standards from Accellera and their application that you can use or plan to use shortly. DVCon concludes on Thursday with a day of in-depth industry sponsored tutorials. My thanks to Tutorial Chair, Aparna Dey, for bringing this all together in conjunction with the Accellera Promotions Committee. Srivastava Vasudevan is the Poster Chair. I have always found conference poster sessions to be a great way to hold a one-on-one conversation with a poster presenter and the DVCon poster sessions are ready to delight you this year. Srivastava has a good lineup for the poster session that will engage you. Vanessa Cooper is the Panel Chair where she has put in place panels that will feature some back-and-forth discussions and debates certain to make us all think. As always, we encourage you to get your questions ready because you are an active part of DVCon panels.

You will find additional program elements interesting as well.

Keynote

Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group (DSG) and System & Verification Group (SVG) at Cadence is the conference keynote. Dr. Devgan’s keynote title is “Tomorrow’s Verification Today.” He is going to review the latest trends which are redefining verification from IP to System-level with an increasingly application-specific set of demands for hardware and software development. I’m certain Dr. Devgan’s keynote will resonate with all your challenges.

Tutorials

Tutorials will be on Monday and Thursday. On Monday, Accellera Day will have a set of tutorials and on Thursday there will be a set of industry-sponsored tutorials. Accellera has three half day tutorials. Monday morning starts with one tutorial, “Creating Portable Stimulus Models with the Upcoming Accellera Standard,” that will cover the emerging Portable Stimulus standard. This tutorial will help you prepare to take advantage of this standard when it is approved by Accellera. The tutorial will be delivered by Portable Stimulus Working Group members so you will get the most current information on the status of the emerging standard. I predict this emerging standard may well be one of the great productivity boosters to design and verification of advanced systems in recent times. At the lunch break, we will have a panel discussion that will give you the opportunity to interact with the Portable Stimulus presenters and those who are working on IEEE P1800.2 (UVM) and the SystemC Design and Verification standard where you will learn about the pending IEEE approval of UVM and advances in abstraction above RTL respectively. After lunch, tutorials on those two last topics will be held.

The industry tutorials on Thursday bring solutions to issues in a way that show the practical application of tools and technology. The Big-3 EDA companies are your tutorial sponsors with topics that include “Reinventing SoC Verification” from Cadence, to a “Only Formal” answer from Mentor Graphics and “Managing Low Power Verification Complexity” from Synopsys. Those topics only scratch the surface as the afternoon industry-sponsored sessions will cover more practical topics that I’m certain you can apply to your current challenges.

Technical Papers & Poster Sessions

On Tuesday and Wednesday the conference technical sessions will be held and topics will rangefrom design verification language specifics, methodology application of UVM, Formal, Analog/Mixed-Signal to system-level considerations with the impact of software on the design of systems, not just hardware. As with past years, the Technical Program Committee had a hard task to select from so many great submissions. A conference will never have room for all papers submitted. As the TPC selected the best from the best, not all good papers were able to make it into the conference. When we could, we tried to make room in the poster sessions. There are almost twenty poster presentations scheduled for Tuesday morning. There will be awards for both best papers and best posters at the end of the day on Wednesday. Please be sure to vote!

Panels

On Wednesday, there will be two panels. The morning panel will be “User’s Talk Back on Portable Stimulus.” While this is an emerging standard, users are already using technology from several companies that have helped drive the standardization effort. It will be great to add your voice from the floor as the panels are going to be open for audience questions too.

The afternoon panel will explore the impact of SystemVerilog on one’s career. Has it been good for you or has it “jinxed” it as the panel title says may have happened. Certainly, SystemVerilog has had many things emerge because of it. Verification IP as a business standardized on the language has flourished and we have all come to leverage it with UVM, the Universal Verification Methodology. This leads me to ask, is “jinxed” a “good” spell that has been cast on your career or something else?

Special Session

From time-to-time DVCon will host some special sessions. This year, Harry Foster has been asked to present “Trends in Functional Verification: A 2016 Industry Study” based on the Wilson Research Group’s 2016 study. The findings from the 2016 study provide invaluable insight into the state of today’s electronics industry.

Exhibitis & Show Floor

Coming together as a community is fostered by the DVCon Expo. The bigger and better exposition will run from Monday evening to Wednesday evening. See the program for specific opening and closing times. The Expo is a great place to catch up with commercial vendors and learn the latest in product developments. It is also great to connect with colleagues and exchange and share information and ideas. Join us for the DVCon U.S. 2017 “Booth Crawl” where after visiting select exhibitors you will be automatically entered for a lucky draw.

All in all, there will be four days of learning, sharing, and industry interactions that will allow you to plan how to apply all this to your own design and verification environment in the months and years ahead. On behalf of all the volunteers and conference management staff we welcome you to DVCon U.S. 2017!

 

Dennis Brophy DVCon U.S. 2017 General Chair