DVCon U.S. 2018 Welcome Message from the Chair
Bigger and Better!
Bigger and Better applies to DVCon U.S. 2018, but the fact is the electronic systems you design and verify grow bigger and better every year as well. It is no accident that DVCon U.S. has grown, too to keep pace with you! I am happy to share many of the details of additions we have made to DVCon U.S. to add topics of importance that are motivated by the designs you are working on today and the systems you are creating for tomorrow. We have been with you at the start of the smartphone, PC and tablet era and are with you now as new huge market potentials are on the horizon for the Internet of Things (IoT), wearable systems and intelligent embedded systems that are on a path to support fully autonomous vehicles.
From Humble Beginnings
We have seen a lot together as DVCon U.S. celebrates its 30th birthday milestone this year! The first VHDL Users Group meeting was held at the 1988 Design Automation Conference in Anaheim, CA USA during a birds-of-a-feather session. From there it has grown to be known as DVCon now being held in the United States, Europe, India and China. After that 1988 meeting, VHDL was joined by Verilog with promotion arms created for both languages. A language war was presided over and peace in a bilingual/multilingual world was embraced. From a small start, a panoply of DVCons now reach thousands of practicing design and verification engineers around the world annually. It is humbling to be part of this growth and success and even more humbling to help all design and verification engineers be that much more productive and successful.
Having been in the industry in 1988, I do recall the planning that went into the 1988 meeting, but, personally, I have no memory of attending it. If you were there in the beginning or perhaps “not yet born” or “barely out of diapers” as would be the case with younger attendees, I can assure you that this event continues to bring users together to raise awareness of design and verification challenges and share solutions from fellow engineers and tool suppliers. It is this exchange of information that brings attendees back year after year. DVCon U.S. 2018 is a highly informative and educational event we hope you will attend.
As General Chair, I am privileged to represent the work of the Steering Committee and Technical Program Committee members. They do most of the work to form the conference content with help from our conference management company, MP Associates. The following are highlights for this year.
Keynote: Christopher Tice, vice president of Verification Continuum Solutions in the Verification Group at Synopsys will deliver this year’s keynote, “Industry’s Next Challenge: The Petacycle Challenge.” This is the first time Mr. Tice will address DVCon. Mr. Tice is a longstanding and respected industry executive who has a focus to drive solutions in fast-growing verticals such as automotive, networking and IoT. Mr. Tice greatly complements this year’s program content and the future we look forward to creating.
Tutorials & Short Workshops: Of the four days of DVCon, the first and last day offer tutorials. New for this year are Short Workshops on the fourth day. The first day of tutorials is colloquially referred to as Accellera Day. This year Accellera sponsors a morning and afternoon tutorial. The morning tutorial will cover its emerging Portable Test and Stimulus standard and the afternoon will focus on the popular Universal Verification Methodology (UVM) and the work Accellera has done to complete its IEEE-1800.2™-2017 (the IEEE name for UVM) compatible reference implementation. On the fourth day of the conference, there will be six tutorials with a large focus in the afternoon on design and verification targeted at autonomous automobiles and the impact of functional safety requirements on those systems. Are there any bets on when and who will be the first person to come to DVCon in a fully autonomous vehicle?
We added the Short Workshop concept to draw more topics to provide attendees more opportunities to join in discussions and learning exercises that would not be as long and comprehensive as full tutorials. The four Short Workshops on Thursday include topics on Deep Learning for the Design & Verification Engineer, Formal Verification, Mutation Coverage for Advanced Bug Hunting and one that will seek to have the design and verification engineer focus on getting the job done without concern that underlying it all is formal technology.
Technical Papers and Posters: From novice to expert, you are covered. Design and verification practitioners are set to cover popular topics in the formal paper presentation sessions and the ever popular poster sessions. The topics covered include UVM, functional and formal verification, high-level synthesis, C/C++/SystemC, assertion based verification, Portable Stimulus, safety critical verification and ISO 26262 fault analysis, advances in low-power design and verification. The RISC-V processor core even makes an appearance with a paper on its UVM-based verification model. You will certainly find something in the program that will help in your daily design and verification activities. You get to vote on best paper and poster awards to recognize the best-of DVCon. Authors are greatly appreciative of the recognition. This year we have shared some best practices for presenters on how they can deliver better presentations. We hope this shows. If this works, we may have made your job to discern the best paper and best poster just that much more difficult.
Panel Discussions: We have two panels this year, and both will be on the third day of the conference. The first panel reflects the issue that has come with the advent of large designs: Big Data. The more and more verification information that is generated, the harder it is to find root causes to problems or system flaws. With so much information being generated, you may find it hard to attain the system coverage you seek. The panel will be a good way for industry experts to explore this more. The second panel will explore the right tool for the hardest verification jobs. This reminds me of the old adage that says “if all you have is a hammer, everything looks like a nail.” The good news for design and verification engineers is that there are many tools to choose from and the panel should help us understand which tool is best for which task. And for both panels, we will be ready and open for questions from the floor. This is your time to speak too!
Exhibits: We have just about every inch of exhibit space covered. This makes for exciting social interactions after the conference program ends, during the evening receptions or during breaks. It is a good venue for business meet-ups when the conference is in session. You will find the latest in EDA tools, design and verification IP and services represented. Armed with what you have learned in the conference setting, the exhibitors will be ready to share their advances that might help you with many of your pressing design and verification issues. Whether you are in the exhibit area or connecting with peers at the hosted lunches, you will have many opportunities to network with your peers and learn from each other.
On behalf of the DVCon U.S. 2018 Steering Committee and Technical Program Committee, I want to thank the hundreds, if not thousands of those who worked on or supported prior conferences from 1988 until today. It is their hard work and dedication that sets the stage for all of us now. I want to acknowledge the ongoing support of conference sponsors and Accellera Systems Initiative for their financial backing.
As you make your way to DVCon U.S. 2018, our conference “front door” is managed by MP Associates who has been the conference committee’s back office the past year to bring this full program to you. I want to thank them for all their work as well.
With that, I look forward to seeing many returning faces and meeting new attendees. I offer each and everyone one of you a hearty welcome to DVCon U.S. 2018! Let’s come and learn, exchange ideas and advance design and verification together.