Committee Member Quotes! They Answer Why You Should Attend DVCon U.S. 2017
Tom Fitzpatrick, DVCon U.S. Program Chair
1. What’s special about the DVCon U.S. 2017 program?
[TF] As always, the DVCon US program reflects the latest trends and hottest technologies in Design and Verification.
2. Anything new or unexpected in the program this year?
[TF] In addition to the keynote by Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and System & Verification Group at Cadence, we have our customary technical sessions with 39 in-depth technical papers, as well as our poster session which gives attendees the chance to interact closely with additional experts on a variety of topics. As a special bonus this year, Harry Foster of Mentor Graphics will present a special session to update everyone on the results of his bi-annual survey of Trends in Functional Verification.
3. Any specific focus or theme attendees can look forward to?
[TF] Given the excitement around the new Portable Stimulus Standard being developed in Accellera, we will be having a tutorial on Monday dedicated to educating attendees on this topic, as well as a “Users Talk Back” panel on Wednesday morning where several experts – some from the Accellera Working Group and some not – will share their thoughts on this important topic.
4. What can attendees hope to learn?
[TF] We will of course have several sessions devoted to UVM and SystemVerilog, including what is sure to be an entertaining panel moderated by Jonathan Bromley of Verilab: " SystemVerilog Jinxed Half My Career: Where Do We Go From Here?" This year we’ll also have sessions dedicated to optimizing all aspects of verification, from low-power and coverage to the overall verification process itself, as well as several sessions on formal verification. We’ll also have sessions on AMS verification, reuse and debug.
5. Why should a design or verification engineer attend DVCon U.S.?
[TF] DVCon has long been the technical (and social) highlight of the year for design and verification engineers. Through the hard work of a large team of dedicated reviewers, we have chosen the best of over one hundred submitted abstracts from deeply knowledgeable colleagues of yours to help you learn how to improve your verification efforts. We also have two days of extended tutorials where you can get an in-depth look at the cutting edge of verification, not to mention the Exhibit Floor where over 30 companies will be demonstrating their latest tools and technologies. In between, there are plenty of opportunities to network, relax and take advantage of a fun and welcoming atmosphere where you can reconnect with old friends and former colleagues or make new friends and contacts. The value of DVCon goes well beyond the wealth of information you’ll find in the Proceedings. Being there makes all the difference.
Vanessa Cooper, Panel Chair
Year after year, I continue to be impressed by the number and quality of the panel submissions that we receive. I believe the audience will find that the two that were selected are both highly relevant and engaging topics. Both panels will be held on Wednesday, March 1.
The first panel, “Users Talk Back on Portable Stimulus” will be moderated by Adnan Hamid of Breker. Portable Stimulus is a new and exciting area of verification and this panel will give users a better idea of what to expect and to question the impact Portable Stimulus will have on verification.
The second panel, “SystemVerilog Jinxed Half My Career: Where Do We Go From Here?” is particularly timely since SystemVerilog is approaching its 15th anniversary. This panel will be moderated by Jonathan Bromley of Verilab. The panelists, along with the audience’s participation, will debate the impact that SystemVerilog has had on the verification industry as well as discuss what future changes would serve us best.
Both panels boast an impressive list of panelists, but I highly encourage the audience to jump in with questions to spur a more spirited conversation. We look forward to seeing you at DVCon U.S.!
Technical Program Committee Member Quotes!
In some ways I am the odd person out. As an academic, I have spent my career working on a lot of CAD tools in advanced application areas. With students I had a simulator up and running for VHDL 7.2 prior to standardization. I come to DVCON to monitor the evolvement of HDL Design and Verification. This is one of the few fields that is constantly evolving and in some ways is an art more than a science.
DVCon has grown substantially over the last few years including its counterparts in India, Germany and soon in China (few months away). From its HDLCon days this one conference has attracted top notch talent across the globe. It is a great place to share thoughts, ideas, listen to panels, attend tutorials and of course the technical papers. From a business perspective it provides a great deal of networking that many of us, entrepreneurs in VLSI, find it hard to miss.
The 2017 edition is very interesting for many DV engineers due to the following key factors:
1. UVM being clearly the most adopted industry standard in our field, every DV engineer is keen to understand what is in store with the upcoming IEEE P1800.2 standard. With a tutorial on this very topic (Monday), I believe the committee has done a great job in organizing a timely update to the attendees. This tutorial also presents an application of this open standard to render itself much easier for RTL Designers to adopt UVM quickly for targeted applications. This part of the tutorial I believe will bring in RTL designers to this tutorial and the event at large.
2. Assertions and formal continue to gain adoption especially due to the recent formal apps making them easy to use. There are at least 3 tutorials that focus on Assertions and Formal approach in the agenda. There are also very interesting papers on assertion-based verification including one from our company titled "Architecting Checker IPs" by Ajeetha Kumari
3. Debug is the new frontier to invest and innovate - given the vast amount of time being spent by engineers everyday on this task. There is a debug tutorial by Synopsys on Thursday and a series of papers on this topic. We also have a poster on "Debug APIs" - highlighting the emerging trends in debug. This would be very interesting for CAD and flow developers trying to increase productivity for their DV teams.
So all-in-all a great technical program lined up for you, see you at the event