DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC, and e, as well as general-purpose languages such as C, C++, Python, PERL, and Tcl. Tools and methodologies include the use of machine learning, open-source software, hardware and architecture, testbench automation, hardware-assisted verification, hardware/software co-verification, formal verification, functional safety and security, transaction-level system design, high-level synthesis, low-power design techniques, 3D chip designs, IP-based SoC design methods, reference flows, and AMS design and verification.
DVCon offers short workshops and tutorials to encourage greater sponsorship participation from companies and exhibitors, especially smaller organizations at an affordable level.
DVCon is a highly targeted venue for engineers addressing major design and verification issues. Submit proposals by September 9.