TECHNICAL SESSIONS
8:15-8:45am
Opening Session
Location: Fir/Oak
9:00-10:30am
Session 1: Mixed Signal
Location:Oak
Session 2: Stimulus Generation
Location:Fir
Session 3: Design
Location: Monterey/Carmel
3:00-5:00pm
Session 5: Testbench Construction
Location: Oak
Session 6: Advanced Techniques
Location: Fir
Session 7: Multi-Language
Location: Monterey/Carmel
POSTER SESSION
36 Posters will be presented!
10:30am-12:00pm
Gateway Foyer
BEST PAPER/BEST POSTER
VOTE NOW!
KEYNOTES ADDRESS
Smart Design from Silicon to Software
Aart de Geus
Chairman & co-Chief Executive Officer
-Synopsys, Inc.
1:30-2:30pm
Location: Oak/Fir
SPONSORED LUNCHEON
Industry Leaders Verify with Synopsys
12:00-1:15pm
Location: Pine/Cedar
At this luncheon, you will hear industry experts share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next project as well as discussions about the latest developments in the verification landscape and groundbreaking technology.
Sponsored by:
NETWORKING RECEPTION
5:00-6:00pm
Bayshore Ballroom
Lively discussion paired with light hors' d'oeuvres and cocktails.
DVCON VIRTUAL RESOURCES
Visit the Virtual Resource Center to access tutorial slides and proceedings.