Session 1: Mixed Signal
Session 2: Stimulus Generation
Session 3: Design
Session 5: Testbench Construction
Session 6: Advanced Techniques
Session 7: Multi-Language
36 Posters will be presented!
BEST PAPER/BEST POSTER
Smart Design from Silicon to Software
Aart de Geus
Chairman & co-Chief Executive Officer
Industry Leaders Verify with Synopsys
At this luncheon, you will hear industry experts share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next project as well as discussions about the latest developments in the verification landscape and groundbreaking technology.
Lively discussion paired with light hors' d'oeuvres and cocktails.
DVCON VIRTUAL RESOURCES
Visit the Virtual Resource Center to access tutorial slides and proceedings.