DVCon U.S. 2018
Best Paper & Poster Winners
7.3 My Testbench Used to Break! Now it Bends: Adapting to Changing Design Configurations
Speaker: Jeffery Vance - Verilab, Inc.
Jeffrey Montesano - Verilab, Inc.
Kevin Vasconcellos - Verilab, Inc.
Kevin Johnston - Verilab, Inc.
12.3 Error Injection in a Subsystem Level Constrained Random UVM Testbench
Speaker: Jeremy Ridgeway - Broadcom Limited
Hoe Nguyen - Broadcom Limited
6.1 Deep Predictive Coverage Collection
Speaker: Rajarshi Roy - NVIDIA Corp.
Chinmay Duvedi - NVIDIA Corp.
Saad Godil - NVIDIA Corp.
Mark Williams - NVIDIA Corp.
4.18 Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages
Speaker: Timothy Pertuit - Hewlett Packard Enterprise
Doug Gibson - Hewlett Packard Enterprise
David Lacey - Hewlett Packard Enterprise
4.16 Fast Track Formal Verification Signoff
Speaker: Mandar Munishwar - Qualcomm, Inc.
Sandeep Jana - Synopsys (India) Pvt. Ltd.
Xiaolin Chen - Synopsys, Inc.
Arunava Saha - Synopsys, Inc.
4.26 Tired of Slow Gate Level Design Verification? Use these Efficient Modelling Styles and Methodology
Speaker: Gabriel Chidolue - Mentor, A Siemens Business
Speaker: Rohit Jain - Mentor, A Siemens Business
Shobana Sudhakar - Mentor, A Siemens Business
Thank you to our Sponsor:
Conference Details 2019
Conference Program & Registration
The committee is working on an exciting event for DVCon U.S. 2019 and will have the complete conference program available in early December.
Plan ahead and book your hotel reservation for the conference now.
DVCon U.S. has a discounted room rate of $214 king/double for February 25 - 28, 2019. The room rate includes complimentary Wi-Fi. The special room rate will be available through February 1, 2019 or until the group block is sold-out, whichever comes first.