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The Design & Verification Conference is looking for submissions for the in-person 2024 Conference and Exhibition. This conference focuses on the practical aspects of design and verification of electronic systems and integrated circuits. This could be applications of languages, tools, methodologies, and/or standards. This could be your chance to help the industry we are all a part of. For those familiar with DVCon, the submission timeline has changed for this year. Please see below for more details.
DVCon honors the Sutherland Best Paper and Best Poster submissions. The awards will be selected by the attendees at DVCon, based on the quality of both the paper and the presentation. So please submit your abstract and join DVCon U.S. 2024!
Please submit your extended abstract – a minimum of 600 words, a maximum of 1,200 words (approximately 2 pages, not including diagrams, figures or tables) – outlining your proposed presentation by Friday, September 15. Full instructions and details for the extended abstract submission process can be found on dvcon.org.
Because of the delayed submission deadline for DVCon U.S. 2024, extensions will not be provided at any point during the submission process. If the guidelines/deadlines are not followed, DVCon will remove your submission.
EXTENDED ABSTRACT SUBMISSION GUIDELINES
The extended abstract should provide enough details so that the Technical Program Committee can evaluate the potential quality of your completed paper and the interest of the DVCon attendees in your presentation.
Proposal Submission Extended Deadline: October 6, 2023 23:59 (GMT -0700)
DVCon US is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, SystemC, PSL, and e, as well as general purpose languages such as C and C++, PERL, Tcl and Python. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, transaction-level system design, high level synthesis, low power design and verification techniques, Functional Safety and Security, 3D chip designs, IP-based SoC design methods, reference flows and AMS design.
Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development, and application of Electronic Design Automation (EDA) tools. Presentations are highly technical in nature, and reflect real life experiences in using these languages and tools.
DVCon is planning to host one highly focused panel discussion. DVCon is looking for a panel that is lively, controversial, and provokes discussion on a specific topic of interest to the community. The panel session should not consist of a paper presentation, but should have plenty of discussion engaging the audience. The panel is scheduled for 1 hour on Wednesday, March 6, 2024.
