Welcome to DVCon U.S. 2023!

DoubleTree by Hilton Hotel San Jose, San Jose, CA, USA

FEBRUARY 27 – MARCH 2, 2023

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.

Important Dates

September 9, 2022

Preliminary Accept/Reject

September 23, 2022

Tutorial, Workshop, and Panel Proposal Submission Extended Deadline

October 14, 2022

Draft Paper Due

October 25, 2022

Tutorial, Workshop, Panel Accept/Reject Notification

October 28, 2022

Final Paper Due

November 18, 2022

Final Paper Accept/Reject

Call for Sponsored Tutorials

Extended Deadline: September 23

Call for extended abstracts

Extended Deadline: August 15

Call for Short Workshops

Extended Deadline: September 23

Call for Panels

Deadline: September 13

Example Topics

VERIFICATION
& VALIDATION

Advanced methodologies and test-benches
Verification processes, regressions and resource management
Debug and analysis of complex designs
Multi-language design and verification
Hardware/Software co-design and co-verification of embedded systems

SAFETY-CRITICAL DESIGN & VERIFICATION

Verification and DO-254 compliance
Automotive ISO 26262 Design and Verification Challenges
Medical or Industrial Verification Challenges
Requirements-Driven Verification Methodologies
IP protection and security

DESIGN AND VERIFICATION REUSE & AUTOMATION

Bridging verification and validation across multiple engines
SoC and IP integration methods and tools
Applications of the Accellera Portable Stimulus Standard
Configuration management of IP and abstraction levels
Interoperability of models and/or tools
High-level synthesis from ESL languages
Bridging virtual prototyping, simulation, emulation and/or FPGA prototyping

MACHINE LEARNING AND BIG DATA

Automating the Optimization of Verification Processes
Coverage metrics and data analysis
Performance modeling and/or analysis

MIXED-SIGNAL DESIGN & VERIFICATION

Mixed-signal design & verification techniques
Real-value modeling approaches
Application of mixed-signal extensions for UVM

LOW-POWER DESIGN & VERIFICATION

Low-power design and verification
Clock domain crossing verification
Power modeling, estimation and management

Gold Sponsor

Best Paper Sponsor

Registration Sponsor

Exhibitors

Conference Sponsors

Global Sponsors

#DVCON-US