• CDC-RDC analysis has evolved as an inevitable stage in RTL quality signoff in the last two decades. Over this period, the designs have grown exponentially to SOC's having 2 trillion+ transistors and chiplet's having 7+ SOC's. Today CDC verification has become a multifaceted effort across the chips designed for clients, servers, mobile, automotives, memory, Al/ML, FPGA etc ... with focus on cleaning up of thousands of clocks and constraints, integrating the SV/\s for constraints in validation environment to check for correctness, looking for power domain and OFT logic induced crossings, finally signing off with netlist CDC to unearth any glitches and corrupted synchronizers during synthesis.

    As the design sizes increased in every generation, the EDA tools could not handle running flat and the only way of handling design complexity was through hierarchical CDC-RDC analysis consuming abstracts. Also, hierarchical analysis helps to enable the analysis in parallel with teams across the globe. Even with all these significant progress in capabilities of EDA tools the major bottleneck in CDC-RDC analysis of complex SOC's and Chiplets is consuming abstracts generated by different vendor tools. Different vendor tool abstracts are seen because of multiple IP vendors, even in house teams might deliver abstracts generated with different vendors tools. 

    The Accellera CDC Working-Group aims to define a standard CDC-RDC IP-XACT model to be portable and reusable regardless of the involved verification tool. 

    As moving from monolithic designs to IP/SOC with IPs sourced from a small/select providers to sourcing IPs globally (to create differentiated products), the quality must be maintained as driving faster time-to-market. In areas where the standards (SystemVerilog, OVM/UVM, LP/UPF) are present, the integration is able to meet the above (quality, speed). However, in areas where standards (in this case, CDC-RDC) are not available, most options trade-off either quality, or time-to-market, or both :-( Creating a standard for inter-operable collateral addresses this gap. 

    This workshop aims to remind the definitions of CDC-RDC Basic Concepts and constraints, as well as the description of the reference verification flow, and addressing the goals, scope & deliverables of the Accellera CDC Working Group in order to elaborate a specification of the standard abstract model. 

    Presenters:

    • Bill Gascoyne, Blue Pearl Software
    • Ping Yeung, Nvidia
    • Chetan Choppali Sudarshan, Marvell
    • Don Mills, Microchip Technology
    • Anupam Bakshi, Agnisys
    • Farhad Ahmed, Siemens EDA
    • Iredamola Olopade, Accellera