The advent of RISC-V has presented verification teams with many new verification challenges. Complex interactions at the system level, that must be considered when developing a RISC-V core, include uncommon scenarios for block level verification teams. As we move towards more system-level verification in general, these types of scenarios will become commonplace. As such, RISC-V verification provides, among many other things, an interesting learning vehicle for general verification challenges to come. 

This workshop will discuss a specific complex, but yet commonplace, verification challenge for any team working on a complex RISC-V core. We will consider the verification of a Memory Management Unit (MMU) that includes virtualization and hypervisor operation. These scenarios need to consider both Single- and Multi-core devices along with an Input Output Memory Management Unit (IOMMU) and uncore IP interaction. 

In this case, scenarios that will be considered will include a broad range of Page Table Entry (PTE) setup cases and page fault cases, with diMerentiated behavior at diMerent privilege levels. Many use cases for the MMU will be included from various data read and write operations and code fetches, up to issues such as self-modifying code. Complex interactions that include a range of Cache Coherency scenarios, RISC-V Weak Memory Ordering (RVWMO) that makes use of the fence instructions, Translation Lookaside BuMer (TLB) invalidation and sfence.vma cases, and many other situations. 

As part of the workshop, a test place with a full range of scenarios will be discussed and considered, and eMicient tests will be shown that provide high coverage, even at the more complex system level. This workshop will be useful for anyone working on RISC-V cores or processor verification, but is also applicable for any verification engineer considering the development of more complex testbenches that extend into system interaction.