Ambar Sarkar - NVIDIA Corp.
Adam Sherer - Cadence Design Systems, Inc.
Mike Borza - Synopsys, Inc.
A System on Chip (SoC) or Application Specific Integrated Circuit (ASIC) is comprised of multiple components referred to as Intellectual Property (IP) blocks or just IP. These blocks come from multiple sources such as internal development teams, IP suppliers, tool-generated IP, etc. Typically, the SoC/ASIC owner integrates multiple IPs from multiple sources, which raises concerns about the security risk. How much risk is the Silicon owner (i.e., Integrator) inheriting? What potential security concerns exist that the Integrator must address to ensure the security objectives of the SoC/ASIC are upheld? The workshop will introduce an emerging new standard called IP Security Assurance (IPSA) to address these concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to highlight IP assets and associated known security weakness entries in a knowledge base for the mitigation implementer to address.
The workshop will focus on the following which is based on the whitepaper:
- Methodology which details the overall concept and workflow along with the individual components, dependencies, and assumptions.
- Security weakness knowledge base that highlights potential IP security concerns.
- OpenCores examples to demonstrate how the methodology applies to real IP cores.
- Summary and Outlook which details the road map and expectations moving forward. This includes integrator's obligations when integrating IPSA-ready IP and suppliers' obligations to sustaining assurance with IPSA-ready IP.
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