March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

MONDAY March 02, 3:30pm - 5:00pm | Oak
KEYWORD: SYSTEMC /C/C++ DESIGN AND/OR VERIFICATION OF SYSTEMS
EVENT TYPE: SHORT WORKSHOP

SESSION 4SW
How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity

Speakers:
Mike Meredith - Cadence Design Systems, Inc.
Stuart Swan - Mentor, A Siemens Business
Matt Bone - Intel Corp.
Rangharajan Venkatesan - NVIDIA Corp.
Organizer:
Ellie Burns-Brookens - Mentor, A Siemens Business

HLS has long promised that it could deliver dramatic productivity by raising the level of abstraction but there have always been questions regarding the fit of this technology and the results that it could achieve vs hand-coded RTL and what an overall HLS design and verification methodology would look like.

This 90-minute tutorial will begin with an introduction to the SystemC Synthesizable Subset and an introduction to basic concepts of how HLS works to go from SystemC/C++ description to quality RTL. It will then leave a majority of the time for the audience to hear from two leading semi-conductor vendors about real-world use-cases and the results they have achieved; Intel and NVIDIA.

Matt Bone of Intel will describe their challenges and successful techniques for design space exploration and tuning of algorithmic and fabric-oriented designs.

Rangharajan Venkatesan of NVIDIA will describe their open-source HLS library, MatchLib, and present a case study for fast prototyping of a Machine Learning accelerator using object-oriented HLS methodology.


Thank you to our Sponsor: