As advanced low-power architectures have become more pervasive in industry, the complexity of these architectures has driven new methodologies for the verification, implementation, and reuse of power intent specifications. Modern low-power designs place requirements that span from enabling more flexible IP design reuse to providing well defined interfaces between analog and digital components in simulation. The IEEE 1801-2024 (UPF 4.0) standard provides several key enhancements that are required to keep pace with these innovations in lowpower design. The workshop will provide an overview of the enhancements to the standard from both a conceptual and a command level. New concepts such as virtual supply nets, refinable macros, and UPF libraries will be introduced, as well as rearchitected features with respect to interfacing between analog and digital simulation and advanced state retention modeling. While the new IEEE 1801-2024 standard provides numerous detailed clarifications and enhancements to the previous version, this workshop will focus on the key changes that will impact most designers and changes that enable new functionality. 
 

In the six years since IEEE 1801-2018 was introduced there have been a number of trends in design that required additional features in the standard to support. Key among these is an increasing need for co-verification of analog and mixed signal content. Another trend is that IP providers are providing pre-verified low-power IP to their customers, but struggle to provide a flexible IP for implementation in multiple design contexts while preserving the verification signoff on the blocks. To address these trends, IEEE 1801-2024 provides new features such as Value Conversion Methods (VCM) and HDL tunneling that help bridge the gap between the analog and digital designs, and the concept of a refinable macro to address the IP reuse requirements. 
 

Real-world usage of the previous standard (IEEE 1801-2018) has prompted clarifications and enhancements that will have a significant impact on users of the standard. For example, the modeling of state retention has been entirely reworked to provide better modeling of the retention power intent and to more accurately define requirements on the retention control signals in each phase of state retention. The new standard also codifies some common design practices to make a clear, more consistent implementation across vendors. The new concept of virtual supplies is one such case. It removes the ambiguity that exists today when supplies are used to provide port constraints or to simplify power state definitions, but do not imply a physical supply net in implementation. 
 

This workshop will introduce these new concepts and their associated commands and provide an overview of the major semantic and syntax changes introduced by IEEE 1801-2024. This understanding will help attendees transition to the new standard and improve the quality of advanced low-power architectures and design environments. 

Authors: 

• John Decker, IEEE P1801 Workgroup Chair
• Daniel Cross, Cadence
• Amit Srivastava, IEEE P1801 Workgroup Vice-Chair
• Lakshmanan Balasubramanian, IEEE P1801 Workgroup Secretary
• Marcelo Glusman, Cadence
• Medaramitta Jeevan, Siemens
• Gabriel Chidolue, Siemens
• Rick Koster, Siemens
• Raguvaran Easwaran, Intel
• Paul Bailey, Nordic Semiconductor
• Progyna Khondkar,  Cadence