• Development of SoC is a flow involving several steps and many times there are multiple iterations to meet the design objectives and performance targets. This flow typically involves the following:

    • Design intent definition by architects 
    • Handling CSR (Control and Status Registers), Memory Maps, Register banks, etc. Users usually define their register specifications in SystemRDL (an Accellera standard), spreadsheets, JSON, CSV, etc. Then they use EDA tools to convert these specifications into DV collaterals, firmware headers, documentation, etc., for the consumption of different teams in the SoC development flow.
    • Design teams create RTLs for desired functionality manually from a feature specification. They also work on power specifications, clock synchronization, constraint analysis and timing closure. The same specification is used by other teams to create the verification testbench to verify the design, headers for firmware development, documentation for validation, etc. Any change in the specification during the process leads to iterations and sometimes rework. 
    • Reusing legacy IPs developed internally, mostly RTL, but also at other abstraction levels (TLM)
    • Using third party IPs (RTL and/or IP-XACT) from different vendors.

    Different teams work on different aspects of SoC design dealing with different formats and a series of EDA tools. Finally, everything needs to be stitched together, integrated and assembled into  the SoC which is then packaged and could be used in products inhouse or delivered to other product companies for further development and integration into a product.

    Successful delivery of any SoC requires numerous exchanges of information and data (IPs) across inhouse teams of hundreds of engineers and vendors. It becomes important to standardize this exchange internally and externally for effective utilization of resources.

    Standardized approach also creates scope for automation to further save upon development cycle time. IP-XACT, being an IEEE standard developed by Accellera, helps to standardize the SoC development flow. The latest version of IP-XACT (1685-2022) along with its rich set of TGI (Tight Generator Interface) API helps not only define standard structure of your design data but also allows programmability for automation using the TGI API.

    This workshop demonstrates effective design automation based on IP-XACT 1685-2022 with two use cases:

    • SoC integration automation based on TGI API
    • Automatic instantiation of NoC based on architect intent and IP-XACT

    Attendees of the workshop will learn the following:

    1. Introduction to IP-XACT
    2. Key features of IP-XACT
    3. What's new in IP-XACT 2022 in brief 
    4. Use case 1: Constructing SoC using IP-XACT and TGI API
      1. IP Packaging 
      2. Constructing SoC using IP-XACT
      3. Capture connectivity using busInterfaces and adhocConnections 
      4. What is TGI
      5. Using TGI for programmability
      6. Using vendor extensions for capturing user defined data
    5. Use case 2: Automatic instantiation of NoC based on architect intent and IP-XACT
      1. Flow overview
      2. System map intent definition by architects
      3. NoC automatic instantiation and connection
      4. Output generation from IP-XACT design (NoC RTL, C Header/Driver, UVM RAL, Documentation)
      5. Next design refinement steps
      6. Best practices in SoC creation using IP-XACT