System Verilog UVM provides an uvm_cmdline_processor class, with methods to parse command line arguments. This allows bench developers to control and configure various aspects of the test bench by passing user values along with the test command. This class serves the purpose of passing int, string etc and parsing them, but does not provide additional smart capabilities like randomization. This paper describes an advanced command line processor, an extension of the UVM class which enables users to pass a combination of range or specific values and specify weights to enable randomization of control knobs. The original functionality of the base class is kept intact and additional features are developed on top of it. The source code will be made available in the appendix section of the paper.