In this workshop, the WG would share the findings, requirements and ideas collected so far and the next step plan for the standardization and would like to receive feedback from the analog/mixed-signal verification community. The UVM-AMS tutorial will also share the latest standardization and technology developments as (being) published in the Accellera UVM-AMS whitepaper.
The following main aspects of the UVM-AMS standard under consideration will be discussed at high level in this Workshop.
A UVM-ASM framework for the creation of analog/mixed-signal verification components and test benches by introducing both extensions to digital centric UVM verification IP classes and also related module-based components to facilitate interactions between the class-based and structural environments.
A set of class-based extensions to UVM related to driver, monitor, scoreboard, etc., to support analog/mixed-signal verification
A set of components and/or packages in SystemVerilog and/or Verilog-AMS to facilitate interactions between the class-based and structural environments and to interface with various types of Analog Design Representations.
A set of Application Programming Interfaces (APIs) to enable the development of modular, scalable, and reusable verification components and test benches, including stimulus, sequence and analysis functions, etc.
A framework for creation of Mixed Signal Verification UVM verification components (UVCs) or extensions of existing UVCs for enhanced stimulus, analysis, monitoring and debug capabilities.