Registration will be open for the full length of the conference and will begin each day approximately 30 minutes before the first session. All attendees must check in at the registration desk to collect a conference name badge. 

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Monterey Carmel Oak Fir Bayshore Ballroom
9:00–10:30 Portable Stimulus
Accellera 		USF-based FMEDA-driven Functional Safety Verification
Cadence 		IP-XACT
Accellera
10:30–11:00 Coffee Break
(Gateway Foyer)
11:00–12:30 Portable Stimulus (Continued)
Accellera 		USF-based FMEDA-driven Functional Safety Verification (Continued)
Cadence 		Hierarchical CDC and RDC closure with standard abstract models
Accellera
12:30–13:30 Sponsored Lunch
(Pine Cedar)
Accellera 		Exhibitor Set Up
13:30–15:00 Automatic generation of Device Driver and Programmer's Reference Manual from PSS
Agnisys 		Streamlining Low-Power Verification: From UPF to Signoff
Synopsys 		Functional Safety
Accellera
15:00–15:30 Coffee Break
(Gateway Foyer)
15:30–17:00 UVM Update & IEEE P3164 Whitepaper Overview: Asset Identification
Accellera 		Streamlining Low-Power Verification: From UPF to Signoff (Continued)
Synopsys 		Your SoC, Your Topology
Arteris
17:00–18:00 Welcome Reception
(Bayshore Ballroom)
Monterey Carmel Oak Fir Bayshore Ballroom
8:00–8:30 Opening Session
(Oak)
8:30–9:00 Coffee Break
(Gateway Foyer)
9:00–11:00 Technical Session #1 (Functional Coverage Closure) Technical Session #2 (AI & ML in Verification) Technical Session #3 (Formal Verification Use Cases)
11:00–12:30 Poster Session
12:30–13:30 Sponsored Lunch
(Pine Cedar)
Cadence
13:30–14:30 Keynote: Addressing the Evolving Landscape of Automotive SoCs
(Oak/Fir) 		Exhibit Hall Open
14:30–15:00 Coffee Break
(Gateway Foyer)
15:00–17:00 Technical Session #4 (UVM Testbenches) Technical Session #5 (Functional Safety and Verification) Technical Session #6 (RISCV Design & Verification)
17:00–18:00 Reception
(Bayshore Ballroom)
Monterey Carmel Oak Fir Bayshore Ballroom
8:00–9:00 Panel: When Will We Be Able to Say, "EDA-GPT, Verify my ASIC"?
(Oak/Fir)
9:00–9:30 Coffee Break
(Gateway Foyer)
9:30–11:00 Technical Session #7 (Requirements Definition and Traceability) Technical Session #8 (Mixed Signal with UVM Verification) Technical Session #9 (SystemVerilog Verification Techniques)
11:00–12:00 Poster Ninja Warrior
(Oak)
12:00–13:30 Sponsored Lunch
(Pine Cedar)
Siemens
13:30–14:30 Keynote: From Chips to Checkered Flags: The Race Towards Real World Innovation
(Oak/Fir) 		Exhibit Hall Open
14:30–15:00 Coffee Break
(Gateway Foyer)
15:00–16:30 Technical Session #10 (Requirements Definition and Traceability) Technical Session #11 (Formal: Liveness and Use Cases) Technical Session #12 (Analog Modeling in SystemVerilog)
16:30–17:00 Break
17:00–17:30 Best Paper Presentation
(Bayshore Ballroom)
17:30–18:30 Reception
(Bayshore Ballroom)
Cascade Donner Siskiyou
9:00–10:30 Data-Driven Design, Verification, Validation, and Signoff Case Studies of RISC-V SoCs
Siemens 		Emulation Moves Into 4-State Logic and Real Number Modeling
Cadence 		SystemC Model Code Generation using Large Language Models
Vayavya
10:30–11:00 Coffee Break
(Bayshore Foyer)
11:00–12:30 Data-Driven Design, Verification, Validation, and Signoff Case Studies of RISC-V SoCs (Continued)
Siemens 		FPGA Prototyping for Large Multi-Die / Multi-Core Designs
Synopsys 		Advanced UCIe-based Chiplets verification from IP to SoC
Cadence
12:30–13:30 Sponsored Lunch
(Pine/Cedar)
Synopsys
13:30–15:00 Expanding role of Static Signoff in Verification Coverage
Real Intent 		RISC-V Core Verification: A New Normal in Verification Techniques
Breker 		Automating the Integration Workflow with IP Centric Design
Perforce
2024 exhibit hall layout.