principlesAbstract:
Efficiently delivering a first-time right RISC-V-based SoC requires a flow that supports every phase of the development process -- from rigorously validating the RTL with simulation and formal methods, to full SoC testing with real world workloads, to specialized C++ or SystemC high-level verification of specialized accelerator IP blocks.
And all of this must come together seamlessly so that the project team has data-driven accountability of their verification coverage and completeness at all times.
In this tutorial, using different open-source RISC-V cores and accelerators for context, we will take you on a detailed journey covering three primary areas:
- High-Level Synthesis (HLS) design and verification: Specialized accelerators are commonly incorporated in RISC-V SoCs in the form of new instructions, co-processors, or bus-based accelerators used to off-load compute intensive software functions into hardware. In this segment, we will show how a HLS D&V flow enables designers to rapidly create and evaluate implementation alternatives to achieve the optimal performance, power, and area (PPA) for their design. HLS with C++ or SystemC delivers both an abstract and a low-level VHDL or Verilog RTL model that can be used in downstream verification phases. Our HLS flow has pre-synthesis design checks to find programming errors, verification coverage, and synthesis issues early, as well as both formal and dynamic simulation to verify correctness between the original algorithm and the synthesized RTL.
- RTL-level design & verification: In this segment we will cover the elements of RTL D&V flows that RISC-V projects often call for above-and-beyond legacy SoCs: scalable, exhaustive verification of custom processor instructions and other novel logic, validating the root of trust and overall security of the RTL design, and verifying the correct integration of peripherals via standard interfaces (e.g. AMBA, PCIe, UCIe, et.al.) We will also demonstrate how recent advances in static formal verification and dynamic simulation technologies can deliver step-function gains in total user productivity.
- Full SoC verification: In this segment of the tutorial, we will explore the complexities of verifying and validating SoCs with real-world stimulus and real workloads. We will show how the Veloce ecosystem provides hardware, software, and systems engineers alike the tools and methodologies to not only shift-left their software development efforts, but also provide visibility and correlation to power profiles, performance, and HW debug. We will discuss the details of what the Veloce Hardware Assisted verification execution platform has in providing a congruent verification experience. Specifically, we will share how to apply the mix of virtual prototype capabilities, hardware emulation and enterprise prototyping technologies, enhanced by easy-to-use apps and solutions, to address challenges common to RISC-V SoCs
Working knowledge of Verilog, SystemVerilog, VHDL, and the principles of code and functional coverage will be assumed.
Instructors:
- Russ Klein – HLS design and verification
- Andy Meier – Hardware-assisted verification
- Erik Jessen – RTL design and verification
- John Hallman – Trust and Assurance verification