Abstract:
RISC-V processor cores, particularly complex application devices, require verification content that explores scenarios not encountered with other blocks, however complex. However, a lot can be learned by examining these content requirements for many verification situations. This workshop will explore a number of techniques employed on RISC-V cores today and consider how they may be applied across a range of designs.
For complex, multi-core, out-of-order devices, instruction compliance and micro-architecture validation is not enough. Platform-level testing such as asynchronous interrupts, complex load-store and other scenarios are required. Coherency is a factor requiring specialized testing, as well as atomic operation, paging, privilege level switching, PMP security validation, the examples go on and on.
The verification content for RISC-V processor multi-cores may be considered in layers. A classic RISC-V (and indeed other processor core) verification environment might start with some base tests, instruction compliance, and micro-architectural validation before employing a broad range of system integration and infrastructure content that ensures the device can efficiently drive an SoC. Performance issues must be evaluated alongside functional areas, data coherency, load store hazards, interrupt mechanisms are just a few of the examples of areas to be tested. Of course, if security, or low power are requirements, this adds more to the verification load.
This workshop will guide attendees through verification content designed to address these and other scenarios critical for core level verification. A range of test techniques designed to fully cover these scenarios in a concurrent fashion to wring out unpredictable corner cases will be detailed, that are used on real designs today. Using the Accellera Portable Stimulus Standard, the construction of reusable, configurable SystemVIP will be examined to show how tests might be set up for a variety of scenarios across multiple projects.
Not working on a RISC-V core? This workshop will expose verification mechanisms that can be applied to a broad range of blocks for many applications. By experiencing the techniques applied to processor verification a lot can be learned for verification in general.
Speakers:
- Adnan Hamid, CTO, Breker Verification Systems
- John Sotiropoulos, Principal Engineer, Breker Verification Systems