Abstract: The emergence of the Universal Chiplet Interconnect Express (UCIe) standard has revolutionized the
electronics industry by enabling the integration of chiplets with diverse functionalities and technology
nodes into complex electronic chips. This advancement has introduced new challenges in RTL (Register-
Transfer Level) design, particularly in managing protocols like PCIe, CXL, and Streaming, as well as
implementing a novel Physical Layer and intricate Die-to-Die adapters. Consequently, the verification
complexities of such designs have grown exponentially.
This workshop delves into effective strategies for optimizing verification efforts and enhancing
productivity when working with UCIe-based designs, spanning from individual blocks to system-level
verification. Attendees will gain practical experience in:
- Seamlessly integrating various UCIe blocks with a Device Under Test (DUT).
- Streamlining the transition from Intellectual Property (IP) to System-on-Chip (SoC) level.
- Measuring and analyzing UCIE based system performance.
- Debugging UCIe related scenarios using advanced tools and methods.
Join us in this workshop to uncover solutions for tackling the challenges posed by UCIe-based designs,
identifying critical bottlenecks, and visualizing the performance impact, ultimately empowering
engineers to create more sophisticated electronic chips efficiently.
Speakers:
- Moshik Rubin, Sr Product Management Group Director, Cadence
- Anunay Bajaj, Sr Principal Product Engineer, Cadence